Modern interacting digital systems are becoming increasingly complex, making it difficult to ensure their actual behavior aligns with design-time expectations, particularly in uncertain or dynamic environments, even when specifications are correct. This misalignment affects system scalability, reliability, and increases maintenance costs.We introduce a conceptual framework for identifying and self-explaining mismatches between expected and observed system behavior, together with an algorithm that generates explanations and case studies that apply the conceptual framework for explanation generation in an interacting digital systems setting.

Decreasing the inference latency of neural networks is crucial in situations where real-time responses are necessary. We propose a new neuron architecture for parallel computations, targeting the MLP implementation on an FPGA. The parallelism in the proposed architecture is exposed through the segmentation of non-linear activation functions into a set of linear segments, delivering highly accurate estimations of the original function. The implementation combines various other optimization techniques, such as fixed-point arithmetics, pipelining, array partitioning, and loop unrolling. For the validation of the proposed architecture using the Xilinx Vitis HLS toolchain, four MLPs with a mix of non-linear activation functions have been implemented and evaluated in comparison to accelerated models produced by the open-source tool hls4ml, a Python package for latency-optimized machine learning inference in FPGAs. Experimental results clearly show that our proposed architecture outperformed the corresponding hls4ml model with up to three times speedups.

The European X-Ray Free-Electron Laser (EuXFEL) relies like other high integrity systems on several sub systems. The Low Level Radio Frequency (LLRF) sub system of the EuXFEL is responsible for the correct acceleration of electron bunches. The LLRF system comprises several embedded components that are directly connected to the accelerator hardware. Due to the high complexity of the LLRF system, unforeseen machine trips occur regularly.In this work we built the basis for a mechanism that automatically identifies faulty behavior of the embedded components. To achieve that, we performed two different experiments, where a faulty behavior was artificially injected to the system. We analyzed the experiment data, performed a feature extraction and applied different machine learning methods. We used basic anomaly detection and basic clustering methods for identifying the faulty data elements. Additionally, we used a support vector machine for modelling the systems behavior. The selected algorithms are compared with respect to their ability to classify LLRF data correctly.

Anomaly detection algorithms solve the problem of identifying unexpected values in data sets. Such algorithms have been classically used for cleaning unlabelled data sets from potentially unwanted values. However, the ability to detect outlying values in data sets can also be used to detect anomalies in systems. Semi-supervised anomaly detection algorithms learn from data for known correct behavior. Such algorithms have been used in various fields, e.g., system security, fault detection, medical applications.In this paper, we use the Area Under the Receiver Operating Characteristic (AUROC) score to evaluate algorithms for semi-supervised anomaly detection when applied to high-integrity distributed digital systems. We identify the relevant parameter for each algorithm and observe how the parameter influences the score and the runtime.

The design of energy- and area-efficient systems is important for modern technology. One approach to increase these efficiencies is approximate computing. During the last years, efficient approximations for combinational hardware components, e.g., adders or multipliers, have been proposed.We focus on quality metrics for the evaluation of approximations in sequential circuits with streaming in- and outputs. We propose the usage of sequence distance metrics for analysis of the sequential behavior after approximation and compare their performance to other metrics like mean errors and accumulated errors. We present case studies on some exemplary circuits. The experimental results show that our sequential metrics provide additional information to common mean errors and for stochastic applications yield the best guidance in selecting approximate sequential circuits.

The problem of generating a minimal implementation of a given Boolean function is called exact synthesis. The parameter to be minimized is often the total number of gates used for the implementation. The exact synthesis engine is considered an essential tool for most state-of-the-art logic optimization flows. In this paper, we present an algorithm that, using enumeration over non-isomorphic graph structures, generates minimal circuits implementing specified Boolean functions using a set of predefined gate types. In our experiments, we show that our prototype implementation of this technique can be compared to state-of-the-art tools for small functions. Moreover, we show that this technique can be parallelized effectively.

We propose Syntax-Guided Property Enumeration, a method for automatically obtaining a set of short and readable temporal logic properties from sequential logic networks. Each property is a temporal logic formula which describes a relation between the primary inputs, the primary outputs, and the latches of the network over time. The approach is applicable to any temporal logic for which decision procedures for model-checking and satisfiability are available. In a case study, we analyze a generic USB controller and compare the results to the well-known previous approach GoldMine. We demonstrate how the flexibility of this approach helps the designer obtain different perspectives of the design under analysis. Useful applications are debugging, reverse engineering, security analysis, or specification mining.

We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design.