Fat D. Ho

dblp:236/4270 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
device modeling
0.412019
2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Electronic design automation › technology computer-aided design
device simulation
0.412019
2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Integrated circuit design › semiconductor device modeling
drift-diffusion model
0.412019
2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019

Methods — techniques the papers use, named apart from their topics

quintic splines · 0.42-d numerical techniques · 0.4
YearPublicationVenuePosition
2019 2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines
abstract
This paper is the first known composition to demonstrate the application of quintic splines in the development of a dual-gate MOSFET model based on the well-known drift-diffusion system of differential equations used in semiconductor analysis. The techniques and methodologies presented advance the current state of the art in this particular area by implementing improved 2-D numerical techniques and avoiding the use of common accuracy reducing assumptions to decrease semiconductor equation complexity and execution time. This results in a model that is valid in all regions of operation, includes Non-Quasi static transient behavior, accounts for short channel effects, and allows researchers to predict the real world manufacturing effects of gate oxide thickness imperfections and applied gate voltage disparities. Model validation was accomplished by comparing simulation results to previously published experimental data for long and short channel devices as well as data generated using an established commercial product. In addition, a subsequent paper submission is planned to demonstrate the application of this modeling method in determining frequency response for simple CMOS circuits.
Scott C. Wolfson, Fat D. Ho
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2