This paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region—without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. This paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

Traditionally, an FPGA vendor's own set of computer-aided design (CAD) tools are used to generate circuits for a given vendor's FPGAs. However, numerous non-vendor CAD tools have been introduced to supplement the vendor-provided tools, allowing novel ideas to be explored and a variety of technical challenges to be addressed. This poster presents Maverick, a stand-alone CAD flow for compiling Verilog to bitstreams for Xilinx 7-Series devices. After an initial configuration design is created with Xilinx's Vivado partial reconfiguration (PR) flow to define a static design and a PR region, the Maverick flow can then compile and map Verilog design into that PR region - without the use of vendor tools. The Maverick flow combines two existing open source projects (Yosys and Project X-Ray) with our own RapidSmith2 tools to form an end-to-end compilation flow. It uses Yosys (synthesis), RapidSmith2 (pack, place, route), and the Project X-Ray tools (bitstream generation), taking Verilog designs as input and generating partial bitstreams as output. Several modifications were made to these existing tools and completely new tools were created, including a new RapidSmith2-based router, as a part of this work. This poster details these CAD steps and shows the results of the CAD flow running on a PYNQ-Z1 SoC's ARM processor to compile a set of HDL designs to partial bitstreams. The resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip system which can both compile HDL designs to bitstreams and then configure them onto its own fabric.