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Pyoungwoo Min

dblp:236/7211 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware test
crosstalk fault testing		 0.112006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
hardware test		 0.112006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › hardware verification and test › VLSI testing
interconnect testing		 0.112006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

test pattern generation · 0.1
YearPublicationVenuePosition
2006 Efficient Interconnect Test Patterns for Crosstalk and Static Faults
abstract
This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, “$6n$” patterns are introduced to completely detect and diagnose both static and crosstalk faults, where “$n$” is the total number of interconnect nets. Then, more economic “$4n + 1$” patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance.
Pyoungwoo Min, Hyunbean Yi, Jaehoon Song, Sanghyeon Baeg, Sungju Park
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1