This paper presents a high-speed 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) featuring tailored bit intervals (TBI). The design employs built-in SAR logic to set delays autonomously, eliminating the need for digital assistance, and thereby reducing both power and area consumption. This approach also effectively shortens the waiting time before lower-bit comparisons, enabling faster conversions. The ADC is simulated in the 16 nm process, occupying only 0.0012 mm2, with post-simulation conducted under various extreme process and temperature conditions. Compared to prior works, our design exhibits notable performance advantages, achieving an ENOB of 7.38 bits at TT 25°C with a power consumption of 6.94 mW. Furthermore, the designed TBI-ADC attains a sampling rate of 1.6 GS/s at FF -40°C, representing a 33% increase over the fastest previously reported single-channel, 1b/cycle, 8-bit SAR ADC.

Ultra-dynamic voltage scaling (UDVS) is a popular trade-off technique between delay and power performance. However, voltage scaling will degrade the radiation-aware reliability of traditional latch obviously. In addition, although the shrinkage of feature sizes results in the reduction of latch area, the occurrence possibility of double node upset (DNU) and triple node upset (TNU) events are increasing. Achieving a good balance among delay, power, area and reliability performance is becoming an important issue in the design of radiation-hardened latches, especially considering the coming commercial aerospace applications. Therefore, this paper proposes a TNU self-recoverable latch with wide voltage range (TRLW), which is low overhead and very suitable for UDVS technique. The TRLW latch is mainly composed of two completely interlocking triangle structures, and is able to self-recover from any possible TNU event. Clock-gated isolated cells are skillfully utilized to avoid current conflict. Meanwhile, six transmission gates are carefully integrated into TRLW latch to reduce the propagation delay$\textit{t}_{d2q}$and critical path delay$\textit{t}_{crit}$. Accordingly, the overall performance of TRLW latch is always excellent from normal voltage to near-threshold voltage (NTV). Simulation results based on 28nm CMOS process show that TRLW latch can achieve complete SNU, DNU and TNU self-recovery in all possible cases, and the soft error rate of TRLW latch only raises by 4.6$\%$when the supply voltage is decreased from 0.9 V to 0.3 V. Moreover, compared with the other reported TNU self-recovery latches, TRLW latch consistently achieves the minimum delay, power, area and delay-power-area product (DPAP) under different process, voltage and temperature (PVT) conditions, and obtains average reductions of 3.43$\times$, 3.03$\times$, 2.66$\times$, 1.40$\times$and 10.83$\times$for$\textit{t}_{d2q}$,$\textit{t}_{crit}$, power, area and DPAP when operating from 0.5 V to 1.0 V.

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

In this paper, a new large dither injection technique is proposed for improving linearity in pipelined analog-to-digital converters (ADCs), without losing the dynamic range of the ADCs and deteriorating the corresponding amplifier's linearity. First, analyses of a proper pipelined ADC's architecture are performed for large dither injection. Then, a 9-bit capacitive digital-toanalog converter (DAC) with split architecture is developed to inject the dither ranging from -511/1024 least significant bit (LSB) to 511/1024 LSB of the first stage. To counteract the consumption of the correction range by the capacitive injection dither, the novel 6-bit complementary DACs embedded in the comparator threshold generation circuit are proposed to realize comparator dither injection. In addition, the dither injection amplitude is configurable for investigating different amplitude's effects on the linearity of the ADC. Finally, the proposed dither injection circuit, together with a 16-bit 150 million samples per second (MSPS) ADC, is implemented in a 0.18-μm CMOS technology. The measured results demonstrate the effectiveness of the proposed techniques. The optimum dither is the 9-bit dither, improving not only the spurious free dynamic range (SFDR) of the small signal by at least 13 dB but also that of the large signal by more than 8 dB compared to the case without dither injection. Moreover, dither injection makes the noise floor clean.