The IEEE 1901 standard for power line communication (PLC) enables simple connection among Internet of Things devices. The forward error correction (FEC) codes specified in the IEEE 1901 standard include low-density parity-check convolutional codes (LDPC-CCs) and Reed-Solomon convolutional concatenated (RSCC) codes. This work introduces an efficient reconfigurable encoder in full compliance with the IEEE 1901 standard. First, we propose a reconfigurable LDPC-CC encoder to fulfill the multirate requirement and improve the architecture by fine-tuned parallelization, which takes full advantage of the characteristics of the codeword structure. Then, for area reduction, the optimization regarding the RSCC encoder is extensively exploited. Moreover, the commonality between the encoders is discovered, and some circuitries are shared to reduce the hardware complexity. Equipped with these techniques, an efficient reconfigurable encoder for the IEEE 1901 standard is developed and implemented with 28-nm technology. Implementation results demonstrate that the proposed encoder can meet the throughput requirement of the IEEE 1901 standard and is both power- and area-efficient.

Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication standards usually have multiple code rates and block lengths. Therefore, reconfigurable LDPC decoders have received widespread attention, which require circular-shift networks to support various expansion factors. Besides, for inputs smaller than the network size, the circular-shift network is desired to process multiple frames in parallel to maximize hardware utilization efficiency. The increasing demands put severe challenges to low-complexity implementations of shift networks, especially for codes with numerous expansion factors, such as 5G LDPC codes. In this brief, we present a universal design of efficient reconfigurable circular-shift networks. Through an ingenious modification on the order of permutations, the generation of control signals is considerably simplified, leading to a significant reduction of area and critical path. Moreover, a hybrid architecture organically integrating different networks is proposed for further complexity reduction. Implementation results under TSMC 90 nm technology demonstrate that the proposed network can achieve 25% area reduction and 46% area-efficiency (AE) improvement over the state-of-the-art ones.

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information storage bit-flipping (ISBF) decoder to solve this problem. Different from the existing bit-flipping (BF) decoders which adopt serial decoding manner, in the ISBF decoder, by storing the previous decoding information, the global maximum-finding operation can be executed in parallel to other decoding operations, significantly shortening the critical path. Moreover, a nonuniform flipping rule is incorporated to achieve a better decoding performance. We also present an efficient architecture to implement the ISBF decoder. The design example demonstrates that compared to other hard-decision BF decoders, the ISBF decoder could provide both the best decoding performance and throughput on BSC.

This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.

Probabilistic gradient descent bit-flipping (PGDBF) is the state-of-the-art hard-decision algorithm for decoding low-density parity-check (LDPC) codes on binary symmetric channel (BSC). However, there still exists a considerable performance gap between the PGDBF algorithm and soft-decision algorithms, especially in the error-floor region. To bridge this performance gap, a tabu-list aided PGDBF (T-PGDBF) algorithm is proposed in this paper. In the T-PGDBF algorithm, a tabu-list is employed to help the decoding escape from trapping sets, which is the main cause of the error-floor phenomenon. The bits which are flipped in the current iteration will be added to the tabu-list to prevent them being flipped in the next iteration. Simulation results show that the T-PGDBF algorithm offers a significant performance gain when compared to the PGDBF algorithm, which can reach that of soft-decision algorithms. We also present the hardware architecture to implement the T-PGDBF algorithm. Synthesis results show that the improved performance offered by the T-PGDBF algorithm can be obtained with a small hardware overhead.