This work presents a CMOS-compatible, energy-efficient, and trainable neuromorphic architecture employing LIF neurons, validated through mathematical analysis of the membrane potential dynamics. It is implemented in a modular$64\times 36$crossbar array for temporal sequential detection of 36 alphanumeric patterns, each represented by an$8\times 8$pixel input. A novel spike mismatch detection cell, implemented in UMC 65-nm CMOS technology, enables pixel-wise comparison using two mutually inhibiting LIF neurons and an output neuron that spikes only on mismatches. Column-wise mismatch spikes encode similarity, while a simplified analog winner-take-all (WTA) logic identifies the best-matching pattern and is capable of identifying both positional and density variations. Each modular cell occupies an area of approximately$608~\mu \text {m}^{2}$, with an average power of$25.82~\mu $W per column and energy of 64.55 pJ per inference (0–$2.5~\mu $s), and Monte Carlo simulations showed process/temperature robustness. An accuracy of >95% was achieved under 2–3 pixel perturbations. Real-time validation with fixed alphanumeric inputs confirmed reliable operation at up to 1 MHz with$0.25~\mu $s setup time. A hardware prototype for the proposed block using discrete ICs (SN7404, CD4007) further demonstrated precise spike generation and effective inhibition.

Object detection and recognition are crucial for autonomous vehicles, surveillance systems, and human-computer interaction. We present a new fully complementary metal-oxide semiconductor (CMOS) circuit-based system for object detection and recognition using a Spiking Neural Network (SNN). Our holistic CMOS circuit integrates neuromorphic elements, including a leaky integrate-and-fire (LIF) neuron model, spike time-dependent plasticity (STDP) memristor synapse, and basic analog and digital building blocks. The learning mechanism is manifested by a completely different approach based on an array of XOR gates to recognize six different objects with 256 × 6 size crossbar arrays. This is the first-ever recognition mechanism of its kind. We also perform handwritten digit recognition using a 64 × 4 size array using grayscale conversion. The proposed system’s robustness is validated through process corner simulations, noise analysis, and temperature analysis. We also show the accuracy of our design for the digit recognition task using a confusion matrix plot, and the accuracy turns out to be 82.5 %. Our pioneering approach using a CMOS memristor-emulator STDP crosspoint array-based architecture achieves minimal energy consumption per neuron block, which amounts to ≈ 2.59 pJ per neuron block and an overall energy budget of 663.66 pJ for the entire system considering the object recognition task.

We present a new CMOS circuit and its successful fabrication of an operational transconductance amplifier (OTA)-CMOS inverter-based memristor emulator and investigate its switching behavior from 5 MHz to 50 MHz. It could be considered the first memristor emulator based on a current mode circuit and an inverter. Primarily, the transconductance of the inverter stage transforms the bias-voltage-dependent transconductance of the OTA into an overall flux-dependent memductance of the memristor. We also demonstrate how performance measures such as frequency response, noise, post-layout simulation, and process corners impact the memristive behavior of the design. The power consumption of the proposed memristor emulator is 2.25 mW. The aforementioned power figure is based on a 1.8 V power supply and calculated on a UMC 180-nm CMOS technology node. Further, using this memristor emulator, we implement a CMOS circuit for spiking signal generation called the Memristive Integrate-and-Fire (MIF) neuron circuit that mimics a biological neuron. As far as we know, a spiking signal generation using a memristor emulator remains unreported. Later on, we went on to realize a MIF neuron based object detection application to bring out the practical significance of the MIF neuron circuit. We have fabricated a chip of the proposed memristor emulator design with the die size of L=$1499.96~\mu \text{m}$, W=$1499.96~\mu \text{m}$, and included its fabrication result to validate the theoretical derivations in the work. At last, we perform an experimental realization of a chaos circuit application with the help of the fabricated chip.

A flux-controlled memristor emulator built with off-the-shelf electronic devices and based on a TiO2model is presented in this article. The circuit proposed in this article uses the current mode approach based analog building blocks such as a second-generation current conveyor (CCII) and an operational transconductance amplifier (OTA) as an active element with few passive elements. The circuit shows a clear fingerprint of an ideal memristor. The offered emulator circuit can be made to operate in incremental and decremental modes and functions well up to 26.3 MHz. Nonvolatility, Monte Carlo sampling, and corner analysis simulations are executed to verify the robustness of the circuit. The functional verification of the presented circuit is performed using the 0.18-μm CMOS parameter at a supply voltage of ±1.2 V. The experimental demonstration is carried out by making a prototype on a breadboard using ICs AD844AN and CA3080, which exhibits a good agreement with theoretical and simulation results. The layout of the circuit, which requires a total chip area of 75 × 70 μm2, is also created. Single/parallel combinations of a memristor, a high-pass filter, and a chaotic system are presented to demonstrate its application.