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Rajesh Pamula 0001

dblp:237/0967 · also Venkata Rajesh Pamula 0001 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2025
0000-0002-4647-0425ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 33% Hardware accelerators and domain-specific architectures · 33% Energy-efficient computing · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › energy-efficient architecture
energy-efficient accelerator
0.312018
Architecture Considerations for Stochastic Computing Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Emerging computing paradigms › approximate and stochastic computing
stochastic computing
0.312018
Architecture Considerations for Stochastic Computing Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
stochastic computing accelerator
0.312018
Architecture Considerations for Stochastic Computing Accelerators · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018

Methods — techniques the papers use, named apart from their topics

voltage overscaling · 0.3ASIC prototyping · 0.3
YearPublicationVenuePosition
2025 Computational Vector Stimulation for Spatially Targeted, Low-Latency Adaptive Neuromodulation With Common-Mode Artifact Suppression
abstract
This paper presents a technique for achieving spatially targeted neural stimulation with suppression of driver nonideality-induced common-mode (CM) artifact in low-latency closed-loop neuromodulation applications. The proposed approach utilizes computationally guided concurrent stimulation across multiple electrodes to achieve spatial selectivity in stimulation. The proposed architecture supports flexible storage of multiple, precomputed vector stimulation patterns in integrated memory. A selected stimulation pattern can be quickly accessed and administered in response to decoded neural activity. Additionally, a combination of the stimulator circuit architecture and mixed-signal current imbalance compensation techniques effectively suppress CM artifacts to below 50 mV. These techniques are demonstrated in a 180 nm HV CMOS test-chip containing 46 stimulation drivers of 26 V compliance and validated through a combination of bench, saline, and in vivo tests.
Arindam Mandal, Diego Peña-Colaiocco, Rajesh Pamula 0001, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe 0001
IEEE Trans. Circuits Syst. I Regul. Pap.3
2018 Architecture Considerations for Stochastic Computing Accelerators
abstract
Stochastic computing (SC) is an alternative computing technique for embedded systems which offers lower area and power, and better error resilience compared to binaryencoded (BE) computation. However, the potential of and general design methodologies for SC in accelerator architectures are not well-understood. In this paper, we evaluate individual SC operations, and end-to-end accelerator architectures to understand when and why SC accelerators can achieve compelling energy efficiency gains. Based on these results, we present general design guidelines that should be considered when building energy-optimal SC accelerator architectures. We also evaluate a fully fabricated ASIC prototype-the first of its kind-to empirically evaluate the error tolerance limits of voltage overscaling (VOS) in SC. Our results show that energy efficiency gains from SC primarily stem from SC's simpler datapaths which require fewer sequential elements compared to BE equivalents. This allows them to achieve energy efficiency gains as high as 2.4x and 30x at 8-bit and 4-bit fixed-point precision, respectively. We also find that VOS can improve the energy efficiency further by up to 1.9x by exploiting SC's error tolerant encoding.
Vincent T. Lee, Armin Alaghi, Rajesh Pamula 0001, Visvesh S. Sathe 0001, Luis Ceze, Mark Oskin
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3