This paper details the design and implementation of a wide-band, digital-controlledinverter-based phase interpolator (PI) for a spin-wave detection circuit. The PI contains input phase generation part for coarse phase tunning, and PI core part for fine phase tunning. Fabricated using 65nm CMOS technology, the circuit operates across a frequency range of 1GHz to 5GHz with a 1V supply. The chip is implemented in 65nm CMOS technology and operates from 1GHz to 5GHz, with 1V supply. The power consumption of the proposed PI core is 1.89mW at 5GHz. The measured differential non-linearity and integral non-linearity are 0.6 LSB and 5.17 LSB respectively at the worst case.

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms(1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only$90~\mu \text{W}$associated with the FLL.

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of -63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of -241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO's phase noise (PN), leading to an in-band PN of -116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2.