This paper presents a 50 Gb/s four-level pulse amplitude modulation 4 (PAM-4) wireline transceiver that incorporates a high-swing PAM-4 driver in the transmitter (TX) and an integrator-based baud-rate linear clock and data recovery (IB-CDR) in the receiver (RX). The PAM-4 driver in the TX employs two types of non-return to zero (NRZ)-current mode logic (CML) drivers. The proposed architecture overcomes the inherent signal-to-noise ratio (SNR) limitations of PAM-4 by generating signal amplitudes greater than the supply voltage (VDD). The RX features an IB-CDR that can determine the phase difference between the PAM-4 signal and the sampling clock using the sign and magnitude of the integrators. Consequently, because the IB-CDR can reduce the requirement for additional threshold voltages and samplers for CDR operation, the RX can achieve a competitive Figure-of-Merit with reduced hardware overhead. Moreover, a dual-loop analog equalizer (DAEQ) is introduced to mitigate inter-symbol interference between the TX and RX. In the DAEQ, one loop increases the peak gain, while another loop controls the system bandwidth. The proposed TX and RX were fabricated using a 28 nm CMOS technology and has a maximum data rate of 50 Gb/s. The prototype with a total area of 0.18 mm2 enables a bit error rate of$10^{-11}$at 15.3 dB attenuation and has a power efficiency of 3.28 pJ/bit.

This study proposes a power-efficient 28-Gb/s single-ended four-level pulse amplitude modulation (PAM-4) transceiver (TRX) for next-generation memory interfaces. In the transmitter (TX), an active-inductor equalizer (EQAI) is utilized, while in the receiver (RX), an amplitude-detection least significant bit (LSB) decoder is employed. In the TX, conventional equalization techniques consume substantial power owing to the inclusion of additional components and strong driving power required to mitigate channel-induced intersymbol interference (ISI). However, the proposed EQAI achieves a bandwidth extension up to the Nyquist frequency through gain boosting while reducing hardware costs and minimizing the driving strength. This results in a simple structure with operational efficiency, facilitating low power consumption and a compact area compared with conventional TX equalizers. In PAM-4 RX, the power dissipation is proportional to the clock buffer and the number of comparators used for data decoding. To improve the hardware cost and the power usage in the RX, the proposed RX design utilizes an amplitude-detection LSB decoder, which reduces the number of comparators and comprises a one-stage structure by detecting the amplitude differences between the reference and input voltages during LSB decoding. This ensures the hardware cost and power consumption improvement while implementing a one-tap direct decision feedback equalizer (DFE). The TRX for memory interfaces is optimized for low-power performance by employing these methods, resulting in a notable energy efficiency of 0.96 pJ/bit. This structure is fabricated using a 28-nm CMOS technology, and the core area of the TRX occupies 0.0053 mm2.

This paper presents a 25-Gb/s single-ended four-level pulse amplitude modulation (PAM-4) transmitter (TX) with an integrated pulse width modulation (iPWM)-based feed-forward equalizer (FFE) and a ratio of level mismatch (RLM)-matched voltage-mode driver for high-speed memory interfaces. The phase-domain iPWM-based PAM-4 FFE is proposed to minimize the input/output (I/O) capacitance by equalizing the PAM-4 data in advance of the pre-driver. The TX bandwidth is increased while achieving superior energy efficiency. Moreover, the RLM-matched voltage-mode PAM-4 driver with a ZQ calibration is proposed to compensate for the impedance variation from the four output levels and improve the output linearity. An RLM control pull-up transistor in the proposed driver obviates the need for a data encoder or passive resistors to improve the RLM and occupies a small area. The proposed single-ended PAM-4 TX was fabricated in a 28-nm CMOS technology and occupies 0.005 mm2. It achieves 0.43 pJ/b at 25 Gb/s and an RLM of 99.3%.

This paper presents a 4-GHz ring-oscillator-based digital sub-sampling phase-locked loop (SSPLL) with an energy-efficient dual-domain phase detector (DDPD). The performance of the digital SSPLL is limited by the quantization noise (Q-noise) of the phase detector (PD), and it requires an analog-to-digital-converter (ADC) and optimally spaced voltage comparators (OSVCs) with a large power and area overhead to reduce the Q-noise. The proposed DDPD efficiently detects a phase error in both the voltage- and time-domains, thereby suppressing the Q-noise while minimizing additional cost. It requires only one comparator in the power-hungry digitally-controlled oscillator (DCO) clock path unlike ADC and OSVCs. Consequently, it achieves a high performance while consuming a small amount of power similar to that of a conventional bang-bang phase detector (BBPD). The proposed SSPLL was implemented in a 28-nm CMOS technology. It consumes 5.35 mW at 4 GHz and occupies an area of 0.014 mm2. The integrated rms jitter is reduced by 25.7% using the proposed DDPD, whereas the overall power dissipation is similar to that of a conventional BBPD-based PLL. The jitter-power FoM1of the prototype SSPLL is −235.9 dB, and the FoM2is −250.9 dB.

This study presents a wireline pulse amplitude modulation-4 (PAM-4) receiver using the least significant bit (LSB) decoding method that uses the offset of comparators. The proposed LSB decoding method can generate the same output as that of a conventional comparator by effectively adding the desired offset voltage to only one of the differential PAM-4 signals. Because the proposed decoding method replaces a 4-input comparator with a 2-input comparator, it can improve the bit error rate (BER) performance of the LSB by as much as the most significant bit (MSB). The predetermined offset is useful not only for LSB decoding but also for the direct decision feedback equalizer (DFE) operation. The differential amplitude and common-mode voltage (VCM) of the PAM-4 signal vary owing to the direct DFE tap coefficient. The modified comparator can generate an appropriate offset voltage without an adaptation loop or a VCM compensator although the PAM-4 signals are changed depending on the DFE tap coefficient. A prototype is fabricated using 28-nm CMOS technology and tested using a 10.29 dB channel attenuation at 10 GHz. The maximum data rate is 40 Gb/s, and the power efficiency and area of the proposed architecture are 1.58 pJ/bit and 0.039 mm2, respectively.

The required data rate of wireline communications has increased; however, channel attenuation limits the data bandwidth. Bit-efficient signaling is an effective and efficient solution because more data can be transmitted at the same Nyquist frequency. Several methods for increasing bit efficiency, such as multi-wire signaling, multi-level signaling, and symbol correlation schemes, have been proposed. Each scheme can generate additional codes by encoding the data. Additional codes can be used to transmit more data or to embed data transitions. In this study, the aforementioned schemes are analyzed, and a method is developed to combine them, maximize the bit efficiency, and ensure the data transition density. For the prototype transceiver, a 4-wire PAM-3 (4W3P) signaling scheme was adopted. The 4W3P signaling scheme can increase the bit efficiency to 200% while maintaining the DC-balanced characteristics. Transceiver building blocks, such as the TX driver, feed-forward equalizer, and analog front-end, were optimized for the proposed signaling scheme. The prototype transceiver was fabricated using 28 nm CMOS technology, occupying 0.012 mm2. The RX was measured using the TX and achieved a BER less than$10^{-12}$at 40 Gb/s over the four wires, with a total transceiver energy efficiency of 1.52 pJ/bit.

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.