This study explores the potential of back-side contact (BSC) technology for enhancing power, performance, and area (PPA) in integrated circuits (ICs). Through metal stack exploration experiments on a 32-bit RISC-V core, the research demonstrates significant PPA gains by optimizing front- and back-side metal (BSM) stack and layer purpose allocation. Key findings include a 2.7% power reduction per added back-side layer for clock routing, a 5.5% frequency improvement with combined front- and back-side clock routing, and up to 14.71% power reduction or 10% frequency increase through metal stack optimization for low-power and high-performance targets, respectively. A similar study on an FPGA was also conducted by optimizing the layer stack configuration to achieve maximum frequency gains of 55.34% or 8.95% in total power consumption, respectively, compared to the baseline of an eight front-side-only layer stack configuration.

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Buried power rails and back-side power grids are promising technology-scaling boosters for advanced CMOS technology nodes. System-level evaluation of these technologies shows tremendous promise from power-performance-area (PPA), IR drop, and dynamic voltage droop perspective. However, several process, device, and architectural challenges must be addressed to realize the full potential of this technology. This article reviews the advancements and challenges in successfully adopting buried power rail and back-side power grid technology.