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Yiwen Geng

dblp:237/1626 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 50% Electronic design automation · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › processing-in-memory
computing-in-memory
0.712023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system · Sci. China Inf. Sci. 2023
Electronic design automation
hardware emulation
0.712023
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system · Sci. China Inf. Sci. 2023

Methods — techniques the papers use, named apart from their topics

chip-in-loop emulation · 0.7
YearPublicationVenuePosition
2023 CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system
Ruihua Yu, Bin Gao 0006, Yiwen Geng, Yuyi Liu, Qingtian Zhang, Jianshi Tang, Hu He 0001, Ning Deng 0008, He Qian, Huaqiang Wu
Sci. China Inf. Sci.4
2021 An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips
abstract
RRAM-based computing-in-memory (CIM) chips have shown great potentials to accelerate deep neural networks on edge devices by reducing data transfer between the memory and the computing unit. However, due to the non-ideal characteristics of RRAM, the accuracy of the neural network on the RRAM chip is usually lower than the software. Here we propose an on-chip layer-wise training (LWT) method to alleviate the adverse effect of RRAM imperfections and improve the accuracy of the chip. Using a locally validated dataset, LWT can reduce the communication between the edge and the cloud, which benefits personalized data privacy. The simulation results on the CIFAR-10 dataset show that the LWT method can improve the accuracy of VGG-16 and ResNet-18 by more than 5% and 10%, respectively, with only 25% operations and 35% buffer compared with the back-propagation method. Moreover, the pipe-LWT method is presented to improve the throughput by three times further.
Yiwen Geng, Bin Gao 0006, Qingtian Zhang, Yudeng Lin, Jianshi Tang, Huaqiang Wu, He Qian
DATE1