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Diya Tang

dblp:237/7931 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
0000-0001-6847-4630ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 49% Energy-efficient computing · 28% Memory systems · 22%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprocessor
3d microprocessors
0.512021
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon · IEEE Trans. Computers 2021
Memory systems
cache management
0.512021
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon · IEEE Trans. Computers 2021
Processor architecture and microarchitecture
chip multiprocessor
0.512021
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon · IEEE Trans. Computers 2021
Energy-efficient computing › power management › power budgeting
dynamic power budgeting
0.412019
GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon · IEEE Trans. Computers 2019
Energy-efficient computing
thermal management
0.112021
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon · IEEE Trans. Computers 2021
Energy-efficient computing › energy-constrained computing
dark silicon
0.112019
GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon · IEEE Trans. Computers 2019
Processor architecture and microarchitecture
multicore design
0.112019
GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon · IEEE Trans. Computers 2019

Methods — techniques the papers use, named apart from their topics

greedy algorithm · 0.9dynamic voltage and frequency scaling · 0.4
YearPublicationVenuePosition
2021 Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon
abstract
Because the increasing power density is limited by the thermal constraint, multi-core integrated systems have stepped into the dark silicon era recently, meaning not all parts of the system can be powered on at the same time. Dark silicon effects are, especially severe for 3-D microprocessors due to the even higher power density caused by the stacked structures, which greatly limit the system performances. In this article, we propose a greedy based core-cache co-optimization algorithm to optimize the performance of 3-D microprocessors in dark silicon at runtime. The new method determines many runtime settings of the 3-D system on the fly, including the active core and cache bank positions, active cache bank number, and the voltage/frequency (V/f) level of each active core, which optimizes the performance of the 3-D microprocessor under thermal constraint. Because the core-cache settings are co-optimized in the 3-D space and the power budgets are computed dynamically according to the running state of the 3-D microprocessor, the new method leads to a higher system performance compared with the existing methods. Experiments on two 3-D microprocessors show the greedy-based core-cache co-optimization algorithm outperforms the state-of-the-art 3-D dark silicon microprocessor performance optimization method by achieving a higher processing throughput with guaranteed thermal safety.
Hai Wang 0002, Wei Li 0216, Wenjie Qi, Diya Tang, Letian Huang, He Tang 0003
IEEE Trans. Computers4
2019 GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon
abstract
Dark silicon phenomenon is significant in today's multi/many-core systems manufactured using new generation technology. In order to enhance performance of dark silicon systems, power budget constrained dynamic optimizations are performed in various ways including dynamic voltage and frequency scaling (DVFS) and task scheduling. However, power budgets given by existing methods are generally over pessimistic, which greatly limit the capability of dynamic performance optimization methods. In order to resolve this problem, we propose a dynamic power budgeting method, called Greedy based Dynamic Power (GDP). Different from existing methods, which are steady state based and ignore active core distributions, GDP formulates the power budgeting problem as a thermal-constrained combinational power optimization problem. To efficiently solve this problem, we propose two new ideas: first, we transform the original power-optimization problem to an easier solving temperature-optimization problem; second, we employ a more efficient greedy based algorithm that finds a sub-optimal active core distribution which maximizes power budget. The new method can consider current temperature states and transient thermal effects, which were ignored by existing methods. Both theoretical studies and experimental results show that GDP outperforms existing methods by providing a higher and less pessimistic power budget with low computing cost and guaranteed thermal safety.
Hai Wang 0002, Diya Tang, Sheldon X.-D. Tan, Chi Zhang 0029, He Tang 0003, Yuan Yuan 0030
IEEE Trans. Computers2