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Mojtaba Abaee

dblp:237/8094 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
0000-0003-2377-6939ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 70% GPUs and heterogeneous computing · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU power management
0.412019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units · ACM Trans. Archit. Code Optim. 2019
Energy-efficient computing
leakage power reduction
0.412019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units · ACM Trans. Archit. Code Optim. 2019
Energy-efficient computing
power management
0.412019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units · ACM Trans. Archit. Code Optim. 2019
Energy-efficient computing
power gating
0.112019
ITAP: Idle-Time-Aware Power Management for GPU Execution Units · ACM Trans. Archit. Code Optim. 2019

Methods — techniques the papers use, named apart from their topics

peek-ahead · 0.4idle-time prediction · 0.4
YearPublicationVenuePosition
2019 ITAP: Idle-Time-Aware Power Management for GPU Execution Units
abstract
Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU—the execution units—frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP , a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period length. We design ITAP to be power-aggressive or performance-aggressive, not both at the same time. Our experimental results on several workloads show that the power-aggressive design of ITAP outperforms the state-of-the-art solution by an average of 27.6% in terms of static energy savings, with less than 2.1% performance overhead. However, the performance-aggressive design of ITAP improves the static energy savings by an average of 16.9%, while keeping the GPU performance almost unaffected (i.e., up to 0.4% performance overhead) compared to the state-of-the-art static energy savings mechanism.
Mohammad Sadrosadati, Seyed Borna Ehsani, Hajar Falahati, Rachata Ausavarungnirun, Arash Tavakkol, Mojtaba Abaee, Lois Orosa 0001, Hamid Sarbazi-Azad, Onur Mutlu
ACM Trans. Archit. Code Optim.6