This work focuses on advancing the security field in the hardware design space by formally defining the problem of Hardware Trojan (HT) detection. The goal is to model HT detection more closely to the real world, i.e., describing the problem as "The Seeker’s Dilemma" (an extension of Hide&Seek on a graph), where a detecting agent is unaware of whether HTs infect circuits or not. Using this problem formulation, we create a benchmark that consists of a mixture of HT-free and HT-infected restructured circuits while preserving their original functionalities. The restructured circuits are randomly infected by HTs, causing a situation where the defender is uncertain if a circuit is infected. Our innovative dataset will help the community better judge the detection quality of different methods by comparing their success rates in circuit classification. We use our benchmark to evaluate three state-of-the-art HT detection tools to show baseline results for this approach. We use Principal Component Analysis to assess the strength of our benchmark, where we observe that some restructured HT-infected circuits are mapped closely to HT-free circuits, leading to significant label misclassification by detectors.

Network-on-chip (NoC) is widely used as an efficient communication architecture in multi-core and many-core System-on-chips (SoCs). However, the shared communication resources in an NoC platform, e.g., channels, buffers, and routers, might be used to conduct attacks compromising the security of NoC-based SoCs. Most of the proposed encryption-based protection methods in the literature require leaving some parts of the packet unencrypted to allow the routers to process/forward packets accordingly. This reveals the source/destination information of the packet to malicious routers, which can be exploited in various attacks. For the first time, we propose the idea of secure, anonymous routing with minimal hardware overhead to encrypt the entire packet while exchanging secure information over the network. We have designed and implemented a new NoC architecture that works with encrypted addresses. The proposed method can manage malicious and benign failures at NoC channels and buffers by bypassing failed components with a situation-driven stochastic path diversification approach. Hardware evaluations show that the proposed security solution combats the security threats at the affordable cost of 1.5% area and 20% power overheads chip-wide.

This paper utilizes Reinforcement Learning (RL) as a means to automate the Hardware Trojan (HT) insertion process to eliminate the inherent human biases that limit the development of robust HT detection methods. An RL agent explores the design space and finds circuit locations that are best for keeping inserted HTs hidden. To achieve this, a digital circuit is converted to an environment in which an RL agent inserts HTs such that the cumulative reward is maximized. Our toolset can insert combinational HTs into the ISCAS-85 benchmark suite with variations in HT size and triggering conditions. Experimental results show that the toolset achieves high input coverage rates (100% in two benchmark circuits) that confirms its effectiveness. Also, the inserted HTs have shown a minimal footprint and rare activation probability.

After almost a decade of waiting, SPEC CPU 2017 was released in 2017. CPU designers have adopted the new benchmarks to evaluate the performance of their designs. Compared to its predecessor SPEC CPU 2006, the average number of code lines, instructions, and memory operations has significantly increased. In this paper, we contrast SPEC CPU 2017 and SPEC CPU 2006 benchmarks regarding performance metrics on a RISC-V processor. Principal Component Analysis (PCA) results show that, with only a few exceptions, the analyzed SPEC CPU 2017 workloads are a subset of SPEC CPU INT 2006 workloads in terms of RISC-V performance metrics. Although the benchmark subsets are very similar, we identified some outliers that would be interesting to use for microarchitecture studies as complementary workloads to SPEC CPU 2006.

Network-on-Chip (NoC) is widely used as an efficient communication architecture in multi-core and many-core System-on-Chips (SoCs). However, the shared communication resources in NoCs, e.g., channels, buffers, and routers might be used to conduct attacks compromising the security of NoC-based SoCs. Almost all of the proposed encryption-based protection methods in the literature need to leave some parts of the packet unencrypted to allow the routers to process/forward packets accordingly. This uncovers the source/destination information of the packet to malicious routers, which can be used in various attacks. In this paper, we propose the idea of secure anonymous routing with minimal hardware overhead to hide the source/destination information while exchanging secure information over the network. The proposed method uses a novel source-routing algorithm that works with encrypted destination addresses and prevents malicious routers from discovering the source/destination of secure packets. To support our proposal, we have designed and implemented a new NoC architecture that works with encrypted addresses. The conducted hardware evaluations show that the proposed security solution combats the security threats at an affordable cost of 1% area and 10% power overheads chip-wide.

Abstract Multilevel cache architectures are widely used in modern heterogeneous systems for performance improvement. However, satisfying the performance and security requirements at the same time is a challenge for such systems. A simple and efficient timing attack on the shared portions of multilevel hierarchical caches and its corresponding countermeasure is proposed here. The proposed attack prolongs the execution time of the victim threads by inducing intentional race conditions in shared memory spaces. Then, a thread‐mapping algorithm to detect such race conditions between a group of threads and resolve them as a countermeasure against the attack is proposed. The proposed countermeasure dynamically monitors races on cache blocks and distributes existing and new threads on processing cores to minimize cache contention. Upon detection of a high contention rate that might be either due to an attack or a natural race condition, two mechanisms, namely cache access‐rate reduction and thread migration, will be used by the countermeasure algorithm to resolve the race situation. Evaluations on SPECCPU 2006 benchmark suite show that the proposed algorithm not only protects the system against the introduced attack but also boosts the overall system performance by an average of 46.35% and 55.92% for the worst and average cases, respectively.

Multi-level hierarchical cache architectures are now being widely used in the design and fabrication of multi and many-core chips. However, when two or more threads race to write their own data into the shared-cache, contentions may happen. This natural conflict seriously aggravates the performance of multi-core systems by showing variant performance in multiple runs of even a same program. In this paper, an efficient thread-mapping algorithm is proposed to minimize the cache race condition between threads of multi-core systems. The proposed algorithm, dynamically monitors races on cache blocks and distributes existing and new threads on cores such that the cache contention is minimized. The proposed algorithm uses instructions per cycle (IPC) parameter to detect conflicting threads on the multi-core system. Upon detection of a high contention rate, two mechanisms of cache access rate reduction, and thread migration are used to resolve the race situation. The first solution is a short term one with negligible performance loss, while the former totally resolves the problem with a relatively higher performance cost. Evaluations of the proposed algorithm are done by the use of AKULA simulator alongside SPEC CPU 2006 benchmark suit. Simulation results show that the proposed algorithm improves system performance by average of 6.12% for the SPEC CPU 2006 benchmark suit.