Demo Data from EDBT 2026 / reviewers in the wild / expert
Stuart S. P. Parkin
dblp:237/9927
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0003-4702-6139ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 78% Storage systems · 20% Integrated circuit design · 2% |
Topics — the 11 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › emerging memory technologies › spintronic memory
racetrack memory |
0.9 | 2 | 2020 | ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0 · ACM Trans. Archit. Code Optim. 2020 Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade · Proc. IEEE 2020 |
Memory systems
non-volatile memory |
0.6 | 3 | 2020 | Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade · Proc. IEEE 2020 ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0 · ACM Trans. Archit. Code Optim. 2020 Magnetically engineered spintronic sensors and memory · Proc. IEEE 2003 |
Storage systems
data placement |
0.4 | 1 | 2020 | ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0 · ACM Trans. Archit. Code Optim. 2020 |
Memory systems
emerging memory technologies |
0.4 | 1 | 2020 | ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0 · ACM Trans. Archit. Code Optim. 2020 |
Memory systems
cache |
0.1 | 1 | 2020 | Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade · Proc. IEEE 2020 |
Storage systems › storage architecture
mass storage system |
0.1 | 1 | 2020 | Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade · Proc. IEEE 2020 |
Memory systems › cache management › storage caching
non-volatile cache |
0.1 | 1 | 2020 | Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade · Proc. IEEE 2020 |
Memory systems › non-volatile memory
magnetic random access memory |
0.0 | 1 | 2003 | Magnetically engineered spintronic sensors and memory · Proc. IEEE 2003 |
Memory systems › non-volatile memory
magnetic tunnel junction |
0.0 | 1 | 2003 | Magnetically engineered spintronic sensors and memory · Proc. IEEE 2003 |
Integrated circuit design › emerging device technologies
spintronic device |
0.0 | 1 | 2003 | Magnetically engineered spintronic sensors and memory · Proc. IEEE 2003 |
Integrated circuit design › analog and mixed-signal circuits
magnetic sensor |
0.0 | 1 | 2003 | Magnetically engineered spintronic sensors and memory · Proc. IEEE 2003 |
Methods — techniques the papers use, named apart from their topics
offset assignment heuristic · 0.4integer linear programming · 0.4genetic search · 0.4spin-valve · 0.0giant magnetoresistance · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a DecadeabstractRacetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today’s technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent developments, RTM has attracted the attention of the computer architecture community that has evaluated the use of RTM at various levels in the memory stack. Recent studies advocate RTM as a promising compromise between, on the one hand, power-hungry, volatile memories and, on the other hand, slow, nonvolatile storage. By optimizing the memory subsystem, significant performance improvements can be achieved, enabling a new era of cache, graphical processing units, and high capacity memory devices. In this article, we provide an overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade. We identify the remaining challenges and give an outlook on its future. Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jerónimo Castrillón, Stuart S. P. Parkin |
Proc. IEEE | 7 |
| 2020 | ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0abstractRacetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%. Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón |
ACM Trans. Archit. Code Optim. | 4 |
| 2003 | Magnetically engineered spintronic sensors and memoryabstractThe discovery of enhanced magnetoresistance and oscillatory interlayer exchange coupling in transition metal multilayers just over a decade ago has enabled the development of new classes of magnetically engineered magnetic thin-film materials suitable for advanced magnetic sensors and magnetic random access memories. Magnetic sensors based on spin-valve giant magnetoresistive (GMR) sandwiches with artificial antiferromagnetic reference layers have resulted in enormous increases in the storage capacity of magnetic hard disk drives. The unique properties of magnetic tunnel junction (MTJ) devices has led to the development of an advanced high performance nonvolatile magnet random access memory with density approaching that of dynamic random-access memory (RAM) and read-write speeds comparable to static RAM. Both GMR and MTJ devices are examples of spintronic materials in which the flow of spin-polarized electrons is manipulated by controlling, via magnetic fields, the orientation of magnetic moments in inhomogeneous magnetic thin film systems. More complex devices, including three-terminal hot electron magnetic tunnel transistors, suggest that there are many other applications of spintronic materials. Stuart S. P. Parkin, Christian Kaiser, Alex Panchula, Kevin Roche, Mahesh Samant |
Proc. IEEE | 1 |