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Congwu Li

dblp:238/0644 · DBLP profile ↗
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1ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Systems and software security · 33% Hardware security and side channels · 33% Cryptographic protocols and secure computation · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › physical attacks
cold boot attack
0.512021
Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory · IEEE Trans. Dependable Secur. Comput. 2021
Cryptographic protocols and secure computation › key management
cryptographic key protection
0.512021
Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory · IEEE Trans. Dependable Secur. Comput. 2021
Systems and software security › exploitation
memory disclosure attacks
0.512021
Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory · IEEE Trans. Dependable Secur. Comput. 2021
Parallel and multicore computing › transactional memory
hardware transactional memory
0.112021
Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory · IEEE Trans. Dependable Secur. Comput. 2021

Methods — techniques the papers use, named apart from their topics

transaction partitioning · 1.0hardware transactional memory · 1.0
YearPublicationVenuePosition
2021 Mimosa: Protecting Private Keys Against Memory Disclosure Attacks Using Hardware Transactional Memory
abstract
Cryptography is essential for computer and network security. When cryptosystems are deployed in computing or communication systems, it is extremely critical to protect the cryptographic keys. In practice, keys are loaded into the memory as plaintext during cryptographic computations. Therefore, the keys are subject to memory disclosure attacks that read unauthorized data from RAM. Such attacks could be performed through software exploitations, such as OpenSSL Heartbleed, even when the integrity of the victim system's binaries is maintained. They could also be done through physical methods, such as cold-boot attacks, even if the system is free of software vulnerabilities. This paper presents Mimosa, to protect RSA private keys against both software-based and physical memory disclosure attacks. Mimosa uses hardware transactional memory (HTM) to ensure that (a) whenever a malicious thread other than Mimosa attempts to read the plaintext private key, the transaction aborts and all sensitive data are automatically cleared with hardware, due to the strong atomicity guarantee of HTM; and (b) all sensitive data, including private keys and intermediate states, appear as plaintext only within CPU-bound caches, and are never loaded to RAM chips. To the best of our knowledge, Mimosa is the first solution to use transactional memory to protect sensitive data against memory attacks. However, the fragility of TSX transactions introduces extra cache-clogging denial-of-service (DoS) threats, and attackers could sharply degrade the performance by concurrent memory-intensive tasks. To mitigate the DoS threats, we further partition an RSA private-key computation into multiple transactional parts by analyzing the distribution of aborts, while (sensitive) intermediate results are still protected across transactional parts. Through extensive experiments, we show that Mimosa effectively protects cryptographic keys against attacks that attempt to read sensitive data in memory, and introduces only a small performance overhead, even with concurrent cache-clogging workloads.
Congwu Li, Le Guan, Jingqiang Lin 0001, Bo Luo, Quanwei Cai 0001, Jiwu Jing
IEEE Trans. Dependable Secur. Comput.1