Modern vehicles integrate an increasing amount of computational functionality, driven by the growing complexity of in-vehicle applications. At the same time, automotive system architectures are becoming more centralized, requiring powerful HPC platforms at the core. These platforms must deliver the performance needed for ADAS, AI, and autonomous driving, while also meeting stringent energy efficiency and safety requirements.The CeCaS project addresses these challenges across a wide range of topics and domains of expertise, including processor design in advanced FinFET technology, the transformation of the E/E architecture, and advanced packaging for automotive supercomputing platforms. Within CeCaS, our work focuses on application-specific accelerator design to enable efficient processing of compute-intensive workloads. In this paper, we present our contributions in this area, including the design of hardware accelerators for both conventional and neuromorphic AI workloads, the development and evaluation of representative AI benchmarks, and the use of virtual platforms for early design-space exploration and hardware/software co-design.

The ability of neural networks to universally approximate any function enables them to learn relationships between arbitrary kinds of data. This offers great potential in information security topics such as protocol reverse engineering (PRE), which has seen little usage of neural networks (NNs) so far. In this paper, we provide a novel approach for implementing PRE with solely NNs, demonstrating a simple yet effective reverse engineering of text-based protocols. This approach is modular by design and allows for the exchange of neural network models at any step with better performing models. The architectures used include a convolutional neural network (CNN), an autoencoder (AE), a generative adversarial net (GAN), a long short-term memory (LSTM), and a self-organizing map (SOM). All of these models combine for a new protocol reverse engineering approach. The results show that the widespread application layer protocols HTTP and FTP can successfully be mimicked by artificial intelligen

A pay-per-use Intellectual Property (IP) licensing model that can protect IPs from multiple participants will benefit the FPGA IP market and Small to Medium Enterprises (SMEs). Existing protection solutions in modern FPGA devices rely on dedicated decryption engines that use cryptographic keys, which require programming them in a trusted environment. Since designs from multiple participants need protection in a typical licensing scenario, it requires a trusted third party for key programming and encryption tasks. These requirements led to the proposition of several licensing schemes; however, they do not address several security and flexibility challenges. Therefore, in this work, we propose a pay-per-device IP licensing scheme that is secure, less restrictive for the system developer and offers protection against malicious IP cores. The scheme relies on a Security Framework (SFW) that provides a Trusted Execution Environment (TEE), which handles key storage, cryptographic operations, and security monitoring. A device running the SFW can be considered a trusted platform that provides a direct secure path for the IP from its vendor to the device's TEE, where it is decrypted, analyzed and, then configured on the programmable logic.