Intellectual property (IP) core reuse serves as a key factor to the rapid development of modern system-on-chips (SoCs) by minimizing time-to-market and manufacturing cost. However, it is crucial to prevent security risks such as IP piracy and over-use while allowing IP reuse. IP watermarking is a viable solution to safeguard the copyright of IP cores through their unique identification. In this article, we introduce PSCMark as an innovative technique for authenticating IPs through the power side-channel characteristic using clock gates. PSCMark seamlessly incorporates a power signature with minimal alterations to the IP core. This is accomplished by leveraging the existing clock gates to alter the dynamic power consumption within the IP (in an SoC) based on a specified challenge. This sharp variation in power attributes upon watermark activation facilitates IP authentication in SoC. Our experimental results show that PSCMark can be robustly/effectively verified, even with the interference emanating from the rest of the functional cores in complex SoCs. We evaluate our technique on several SoC benchmarks of varying size (i.e., MIPS, openMSP430, OR1200) and demonstrate its effectiveness in proving IP ownership with high detection resolution. We also provide silicon validation by implementing PSCMark across these benchmarks using the Artix-7 FPGA board. Furthermore, PSCMark ensures a subtle and obfuscated watermarking of IP cores, enhancing its resistance to detection, removal, or modification.

Fault-injection attacks (FIAs) represent a wide-spread and potent method of compromising the integrity and confidentiality of integrated circuits (ICs) and electronic systems. These attacks include voltage/clock glitching, electromagnetic (EM) interference, laser, and optical injection. One promising defense strategy is intrusion detection, which uses sensors to monitor and capture the effects of such attacks. However, the diversity of these attacks has led to the development of specialized sensors for each attack type, posing challenges in terms of feasibility and overhead. This article introduces a universal solution for efficiently detecting prominent FIAs using a lightweight on-chip delay-based fault-to-time converter (FTC) sensor. The proposed sensor functions by translating the consequences of fault attacks into measurable “time” differentials. This design is readily implementable on both field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platforms. The sensor placement considers the most vulnerable elements in the design to fault attacks to position them closely to those locations for extracting the best sensitivity to delay changes. We illustrate the sensor’s responses to major FIAs, demonstrating its ability to differentiate between nominal and fault conditions. The overhead analysis also highlights the sensor’s minimal resource utilization in FPGA implementations. We also explore the sensor’s response to environmental variations for proper characterization.

Oracle Database In-Memory (DBIM) provides orders of magnitude speedup for analytic queries with its highly compressed, transactionally consistent, memory-optimized Column Store. Customers can use Oracle DBIM for making real-time decisions by analyzing vast amounts of data at blazingly fast speeds. Active Data Guard (ADG) is Oracle's comprehensive solution for high-availability and disaster recovery for the Oracle Database. Oracle ADG eliminates the high cost of idle redundancy by allowing reporting applications, ad-hoc queries and data extracts to be offloaded to the synchronized, physical Standby database replicated using Oracle ADG. In Oracle 12.2, we extended the DBIM advantage to Oracle ADG architecture. DBIM-on-ADG significantly boosts the performance of analytic, read-only workloads running on the physical Standby database, while the Primary database continues to process high-speed OLTP workloads. Customers can partition their data across the In-Memory Column Stores on the Primary and Standby databases based on access patterns, and reap the benefits of fault-tolerance as well as workload isolation without compromising on critical performance SLAs. In this paper, we explore and address the key challenges involved in building the DBIM-on-ADG infrastructure, including synchronized maintenance of the In-Memory Column Store on the Standby database, with high-speed OLTP activity continuously modifying data on the Primary database.