On-device learning allows AI models to adapt to user data, thereby enhancing service quality on edge platforms. However, training AI on resource-limited devices poses significant challenges due to the demanding computing workload and the substantial memory consumption and data access required by deep neural networks (DNNs). To address these issues, we propose utilizing embedded dynamic random-access memory (eDRAM) as the primary storage medium for transient training data. In comparison to static random-access memory (SRAM), eDRAM provides higher storage density and lower leakage power, resulting in reduced access cost and power leakage. Nevertheless, to maintain the integrity of the stored data, periodic power-hungry refresh operations could potentially degrade system performance. To minimize the occurrence of expensive eDRAM refresh operations, it is beneficial to shorten the lifetime of stored data during the training process. To achieve this, we adopt the principles of algorithm and hardware co-design, introducing a family of reversible DNN architectures that effectively decrease data lifetime and storage costs throughout training. Additionally, we present a highly efficient on-device training engine named CAMEL, which leverages eDRAM as the primary on-chip memory. This engine enables efficient on-device training with significantly reduced memory usage and off-chip DRAM traffic while maintaining superior training accuracy. We evaluate our CAMEL system on multiple DNNs with different datasets, demonstrating a 2.5× speedup of the training process and 2.8× training energy savings than the other baseline hardware platforms.

Modern and miniaturized ASICs enable the development of anatomically constrained applications within the biomedical framework, such as smart contact lenses. Recent works report lenses receiving power and communicating through inductive coupled links. However, the efficiency of an inductive link depends highly on alignment and distance between coils, thus encouraging the exploration of other techniques to power and communicate a smart contact lens. Intra-body links emerge as an alternative to inductive ones for wearable devices, with promising path-loss results reported in previous works. Here, we evaluate the feasibility of powering a smart contact lens through an intra-body link. We propose a simplified 3D-FEM human-head model to estimate channel losses in a real contact lens situation. Then, we validate the pathloss estimations on the head through a human arm experiment, and comparison against a simplified 3D-FEM human-arm model. Based on our analysis, we estimate retrieved power of μW level, demonstrating the feasibility of using an intra-body link to power a smart contact lens.

Modern system-on-chip (SoC) applications commonly comprise multiple voltage domains to save power consumption according to the required circuit performance. Level shifter (LS) blocks usually interface these power domains to guarantee fitting voltage levels for the control signals among low supply and high supply voltage domains. Using only thin-oxide transistors for LS implementations enables their subsequent integration into the digital domain of an SoC and enhances circuit speed performance. Nevertheless, thin devices entail overvoltage issues when the voltage difference between the supply domains to be communicated is large, e.g. during the SoC's power-up sequence. Here we propose an LS architecture along with a three-devices protection scheme to avoid powering-up overvoltage issues, which have been neglected by reported LS works, validated through simulations. The results disclose a maximum operating frequency of 400MHz and an average energy-per-transition of 470fJ.

This paper introduces a family of three resistor-less low-power, low-area and trim-free current references with low PVT sensitivity. The proposed current sources achieve tens of nano-Ampere current consumption with a temperature coefficient down to 182ppm/°C. The proposed family of current sources are enabled to operate within the 3.3V I/O voltage domain, to avoid additional power consumption from internal regulation, and they are implemented in a 180nm standard logic CMOS process.