As integrated circuit (IC) designs continue to scale in complexity, global routing faces increasing challenges in managing timing and congestion simultaneously. This paper proposes a GPU-accelerated global routing framework that effectively balances timing optimization and congestion mitigation. The proposed framework begins with a preprocessing stage that partitions ultralarge nets, followed by timing path construction, and decomposes nets based on estimated pin slack to enhance scalability and timing sensitivity. For critical nets, we propose a timing and congestion driven GPU-accelerated hybrid 3D pattern routing method. Specifically, an Elmore-based timing weight calculation method is proposed to efficiently capture the timing criticality of routing paths, and the resulting weights are ordered for more targeted and effective timing optimization. Then, a well-designed cost scheme is proposed to better balance timing and congestion. Finally, we develop a GPU-accelerated hybrid 3D pattern routing strategy that combines L -shape and sparse Z -shape patterns to improve routing efficiency. After routing critical nets, the remaining non-critical nets are routed using a congestion-driven GPU-accelerated routing engine that supports flexible detours to alleviate congestion and utilize residual routing resources. Compared with the champion of the ISPD 2025 contest, experimental results on the ISPD 2025 contest benchmarks show that our algorithm achieves 19.4% better weighted scores and 1 6. 2 % faster runtime.

Open-source electronic design automation (EDA) shows promising potential in unleashing EDA innovation and lowering the cost of chip design. The open-source EDA toolchain is a comprehensive set of software tools designed to facilitate the design, analysis, and verification of electronic circuits and systems. We developed a physical design EDA toolchain (named iPD) from netlist to GDS-II, including design, analysis, and verification. iPD now covers the whole flow of physical design (including floorplan, placement, clock tree synthesis, routing, timing optimization etc.), part of the analysis tools (timing analysis and power analysis), and part of the verification tools (design rule check). For more friendly support EDA research and development and chip design, we design a reliability, extendibility, ease-of-use, and feature richness physical design toolchain. This paper introduces the software structure, functions, and metrics of the iPD toolchain.

In this paper, we present an improved electrostatics-based analytical method for fixed-outline floorplanning, which incorporates module rotation and sizing driven by wirelength. To accurately compute the density function after module rotation, we propose a novel density calculation algorithm based on line drawing and polygon clipping algorithms commonly used in computer graphics. By using this algorithm, we are able to accurately compute the density function after module rotation without adding any complexity. Moreover, we propose a module legalization algorithm by adding module sizing and module rotation after the existing constraint graph adjustment step. Furthermore, we adopt a linear programming to minimize wirelength to improve the quality of the results. Experimental results demonstrate that our floorplanning algorithm achieves at least 5.9% and 11% reduction in half-perimeter wirelength on the HB+ and ami49_x benchmarks, respectively, compared to state-of-the-art floorplanners.

Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine definitely has a positive impact on chip design speed, quality, and performance. In this article, we present a novel mathematical model to characterize nonoverlapping of modules, and propose a flat fixed-outline floorplanning algorithm based on the VLSI global placement approach using Poisson’s equation. The algorithm consists of global floorplanning and legalization phases. In global floorplanning, we redefine the potential energy of each module based on the novel mathematical model for characterizing nonoverlapping of modules and an analytical solution of Poisson’s equation. In this scheme, the widths of soft modules appear as variables in the energy function and can be optimized. Moreover, we design a fast approximate computation scheme for partial derivatives of the potential energy. In legalization, based on the defined horizontal and vertical constraint graphs, we eliminate overlaps between modules remained after global floorplanning, by modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+, and ami49_x benchmarks show that, our algorithm improves the average wirelength by at least 2% and 5% on small and large-scale benchmarks with certain whitespace, respectively, compared to state-of-the-art floorplanners.