The causal behavior of Quasi Delay-Insensitive (QDI) circuits may get compromised under the effects of single event transients (SETs). To address the issue, the research community already made efforts in different directions, like with modular redundancy, or shortening the data accepting windows of buffer templates. Nevertheless, in non-modular techniques, the focus remains towards the buffers and combinational logic. Most of the time the conditional control elements, namely Multiplexer and De-multiplexer, are not explicitly addressed. However, for the event-driven behavior these elements are also realized with a storage element called Muller C-element (MCE), so in principle these elements also require special consideration to improve the overall fault tolerance of the circuit. In this article we first analyze the error contribution of these elements during single event transient (SET) strikes and then present a hardening technique to mitigate these effects. The focus is to utilize the inherent fault-tolerance properties of QDI circuits. For better coverage of scenarios we test our technique with two different target circuits, an 8-bit Arithmetic Logic Unit (ALU) circuit designed in a simple linear fashion and a 16-bit iterative multiplier. The analysis includes the state-of-the-art buffer template with one of its SET hardened derivatives named$\Delta$. The findings suggest 40% improvement in tolerance towards SETs with$\Delta_{-}E$, our proposed template with resilient conditional control elements.

Due to their unbounded data accepting windows asynchronous circuits seem to be more susceptible to environmental effects than their synchronous counterparts with their strict data latching protocol. The technology advancement makes single event transients (SETs) more of a concern towards reliable operation.To better understand the properties of the mentioned classes we present their behaviour under the influence of SETs in a more detailed view that helps to visualize their unseen characteristics. For comparison we propose a way of fault injection where the length of a fault pulse is not fixed, calculated based on maximum gate delay, but related to the circuit's computation steps instead.The analysis concludes that asynchronous quasi delay-insensitive (QDI) circuits show better resilience against SETs due to two main reasons: (1) if realized with a 4-phase handshake protocol they are 95 to 97% resilient to negative fault pulses (2) the susceptibility of a circuit is largely unchanged for increasing fault length because of the causality underlying the QDI principle.Our analysis provides insights leading towards more resilient QDI circuits: if we only make a circuit or specific gates better resist "1" faults, we are fully resilient towards the single event transient (SET)s because "0" faults are already filtered out by its inherent behaviour. This is also beneficial for area efficiency; as asynchronous circuits often require already double or more area and computation time compared to synchronous circuits, adding extra SET mitigation with double-up or other buffer redundant techniques tends to result in painful overheads. Being able to focus the protection to "1" faults, as indicated by our analysis, can hence yield important savings.

AµFLIPS is an asynchronous microprocessor with novel pipeline register organization to resolve data and control hazards using synchronous hazard resolving schemes. Existing works claim that mechanisms for handling data and control hazards in synchronous systems are not directly applicable to asynchronous pipelined processors, because of distributed control nature of the latter. As a result of that, most asynchronous equivalents of MIPS propose novel hazard resolution methods, adding an overhead in terms of performance and complexity. In this work, we build a counter narrative by proposing a novel pipelined register organization that maintains synchrony with a flexible clock generator instead of the rigid clock, which also allow us to utilize the synchronous hazard resolving methods. Our simulation results – using Balsa – suggest 20.8% improvement in execution time as compared to one of the existing asynchronous processors.

QDI circuits are robust towards timing issues, but this elasticity makes them vulnerable in value-domain fault scenarios because data-accepting windows are flexibly defined by the handshakes, and during these windows any data transition gets latched, even those originating from single event transients. As a solution, locking the data-accepting windows after the first transition contributes to robustness, but still needs consideration. We examine WCHB variants called Interlocking-WCHB and Input/Output-Interlocking-WCHB in this respect. To highlight the relevant error triggering conditions, we chose two target circuits to investigate the behavior in detail: FIFO and pipelined multiplier. Based on the experimental results we investigate the observed errors to understand the main cause of their generation and propagation. We highlight the problematic scenarios and propose modifications in buffer styles that resolve most of these while minimizing the area overhead to 50%.