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Matthew Casias

dblp:238/5433 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 87% Reconfigurable computing and FPGAs · 13%
Software engineering, system software, and programming languages
1 paper
Debugging and program repair · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Debugging and program repair
fault localization
0.412019
Debugging Support for Pattern-Matching Languages and Accelerators · ASPLOS 2019
Hardware accelerators and domain-specific architectures › pattern matching accelerator
automata processor
0.412019
Debugging Support for Pattern-Matching Languages and Accelerators · ASPLOS 2019
Hardware accelerators and domain-specific architectures
interactive debugging
0.412019
Debugging Support for Pattern-Matching Languages and Accelerators · ASPLOS 2019

Methods — techniques the papers use, named apart from their topics

variable inspection · 0.8step-through debugging · 0.8human study · 0.8
YearPublicationVenuePosition
2019 Debugging Support for Pattern-Matching Languages and Accelerators
abstract
Programs written for hardware accelerators can often be difficult to debug. Without adequate tool support, program maintenance tasks such as fault localization and debugging can be particularly challenging. In this work, we focus on supporting hardware that is specialized for finite automata processing, a computational paradigm that has accelerated pattern-matching applications across a diverse set of problem domains. While commodity hardware enables high-throughput data analysis, direct interactive debugging (e.g., single-stepping) is not currently supported. We propose a debugging approach for existing commodity hardware that supports step-through debugging and variable inspection of user-written automata processing programs. We focus on programs written in RAPID, a domain-specific language for pattern-matching applications. We develop a prototype of our approach for both Xilinx FPGAs and Micron's Automata Processor that supports simultaneous high-speed processing of data and interactive debugging without requiring modifications to the underlying hardware. Our empirical evaluation demonstrates low clock overheads for our approach across thirteen applications in the ANMLZoo automata processing benchmark suite on FPGAs. Additionally, we evaluate our technique through a human study involving over 60 participants and 20 buggy segments of code. Our generated debugging information increases fault localization accuracy by 22%, or 10 percentage points, in a statistically significant manner (p=0.013).
Matthew Casias, Kevin Angstadt, Tommy Tracy II, Kevin Skadron, Westley Weimer
ASPLOS1