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Hojin Seo

dblp:238/6202 · DBLP profile ↗
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3ranked-venue papers
1as first author
1since 2021 · last 2024
0009-0008-3485-9960ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Databases, data mining, and information retrieval
1 paper
Query processing and optimization · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Query processing and optimization
iterative query processing
0.412019
Iterative Query Processing based on Unified Optimization Techniques · SIGMOD Conference 2019
Query processing and optimization
cost model
0.112019
Iterative Query Processing based on Unified Optimization Techniques · SIGMOD Conference 2019

Methods — techniques the papers use, named apart from their topics

query motion · 0.4loop-invariant code motion · 0.4
YearPublicationVenuePosition
2024 A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow
abstract
Object detection models have demonstrated outstanding performance in terms of accuracy. However, mapping convolutional neural network-based object-detection models to memory and computing-constrained devices is still challenging, which commonly leads to accuracy degradation and long latency. To address the problem, this work presents a design methodology to map the YOLOv3-tiny model onto a small FPGA board, in this case the Nexys A7-100T, which only has 0.5 MB on-chip SRAM and 240 DSPs. First, we design four identical MAC arrays to maximize the throughput by utilizing both DSPs and LUTs. Second, to exploit the MACs fully, we propose a dynamic data reuse scheme that handles inter-layer and intra-layer executions effectively under a small on-chip SRAM footprint. To this end, the proposed accelerator achieves an inference speed of 76.75 frames per second and throughput of 95.08 GOPs at 100MHz and consumes power of 2.203W. Specifically, it achieves a hardware utilization rate of 82.53%, thus significantly outperforming current YOLOv3-tiny accelerators.
Minsik Kim 0006, Kyoungseok Oh, Youngmock Cho, Hojin Seo, Xuan Truong Nguyen
IEEE Trans. Circuits Syst. I Regul. Pap.4
2020 An effective graph summarization and compression technique for a large-scaled graph
Hojin Seo, Kisung Park 0001, Yongkoo Han, Hyunwook Kim 0002, Kifayat-Ullah Khan, Young-Koo Lee
J. Supercomput.1
2019 Iterative Query Processing based on Unified Optimization Techniques
abstract
Hybrid transactional and analytical processing (HTAP) systems like SAP HANA make it much simpler to manage both operational load and analytical queries without ETL, separate data warehouses, et al. To represent both transactional and analytical business logic in a single database system, stored procedures are often used to express analytical queries using control flow logic and DMLs. Optimizing these complex procedures requires a fair knowledge of imperative programming languages as well as the declarative query language. Therefore, unified optimization techniques considering both program and query optimization techniques are essential for achieving optimal query performance. In this paper, we propose a novel unified optimization technique for efficient iterative query processing. We present a notion of query motion that allows the movement of SQL queries in and out of a loop. Additionally, we exploit a new cost model that measures the quality of the execution plan with consideration for queries and loop iterations. We describe our experimental evaluation that demonstrates the benefit of our technique using both a standard decision support benchmark and real-world workloads. An extensive evaluation shows that our unified optimization technique enumerates plans that achieve performance improvements of up to an order of magnitude faster than plans generated by the existing loop-invariant code motion technique.
Kisung Park 0001, Hojin Seo, Mostofa Kamal Rasel, Young-Koo Lee, Chanho Jeong, Sung Yeol Lee, Chungmin Lee, Donghun Lee 0001
SIGMOD Conference2