Predicting the Single-Event Effects in integrated circuits before their fabrication and ultimately estimating their cross-section would be of much interest to the space industry. For high-performance analog and mixed-signal circuits, radiation-hardening design flows routinely include Single-Event electrical simulation to identify the most sensitive nodes. If we can identify the sensitive area of the circuit to the PN-diodes connected to the sensitive nodes, we should thus be able to get an estimate of the cross-section. In this work, we show that this is far from being reality by comparing the results of electrical simulations to the cross-sections obtained by radiating a rad-hard reference generator for a high-performance ADC with Heavy Ions. A deep analysis of the results suggests that there are unmodelled effects at stake that dominate the experimental cross-section.

One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.

This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming$LC$package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.