This paper presents the design of a 128 GS/s 64x time-interleaved SAR ADC, featuring an ultra-wideband two-rank hierarchical track-and-hold architecture maintaining 62 GHz bandwidth in 22nm CMOS FD-SOI technology. To achieve both, high bandwidth and concurrently adequate sampling linearity, an inductively peaked input network and first-stage source follower with pseudo-differential gain coupling is used, taking advantage of a dual -0.5V and 0.9V power supply. The front-end T/H also utilizes a mix of static and dynamic body-biasing techniques enabled by the 22nm CMOS SOI technology to further improve the linearity and signal gain. Each second-level buffer drives four 6-bit asynchronous loop-unrolled SAR ADCs at a conversion rate of 2 GS/s, using speed-optimized dynamic logic cells and MDAC redundancy to fulfil the sampling speed requirements. Time-interleaving mismatch effects such as gain, offset and sample skew errors are calibrated off-chip. The total signal bandwidth across the input network, first-level buffer and T/H stage exceeds 62.2/53.9 GHz and the ADC achieves a SNDR of well above 35.5/32.3 dB up to 19.7 GHz as well as 31.7/28.6 dB up to Nyquist-frequency in TT/SS corner.

This paper presents an 11-bit 12GS/s 4x timeinterleaved beam-forming ADC for a 2x2 antenna array in a 22nm FDSOI CMOS process. The RF-input is buffered with a push-pull source-follower providing both high linearity and high-bandwidth. The receiver utilizes sample-based beam-forming with a true time-delay generated from a clock delay network with uniform 11.9ps time-steps. Thus, all inputs are sampled phase-aligned without any phase-shifter in the RF-path. A chargebased summation enables a low-power beam-forming functionality without any wave-length dependencies. The summed output is buffered by a push-pull back-end buffer with cascodes providing a high-linearity. In total, 24x 11-bit 500MS/s SAR subADCs digitize the summed output of the beam-former. Time-interleave sample-phase mismatch can be calibrated with a 30fs step-size. The ADC achieves a voltage gain of 8.55dB in steering direction. An overall SFDR and SNDR above 68dBc and 55dB respectively is achieved. Only a total of 99.5mW per antenna is drawn.

In this paper, a novel charge pump for sub-sampling phase-locked loops (SSPLLs) is presented. Contrary to the conventional charge pump, the proposed implementation eliminates the previously-required pulser. This is achieved by using all sample data from the ping-pong sub-sampling phase detector as opposed to only every second point, which enables the charge pump to run pseudo-continuous. This virtually raises the reference frequency by a factor of two, which is beneficial for the phase noise performance of the phase-locked loop while fulfilling the requirements for bandwidth of reference buffers, switches etc. Furthermore, eliminating the pulser enables a highly power-efficient charge pump design, leveraging higher SSPLL FoM. The proposed charge pump is implemented in a 22-nm fully-depleted silicon-on-insulator technology. The power and area consumption are reduced by roughly 80% and 55%, with similar effective gain, noise and offset performance to the conventional design.

This paper presents the design of a subsampling wideband 500 MS/s 12 Bit successive-approximation-register (SAR) analog-to-digital converter (ADC) with sub-2 radix split- capacitor array (SCA). The presented ADC is designed as a sub-ADC for a sample-and-hold-less (SAH-less) 8 GS/s time-interleaved (TI) ADC. In addition to the required 16 ADC channels, two additional SAR lanes enable pseudorandom binary sequence (PRBS)-driven channel scrambling. A 1.81 radix is used to achieve 12 Bit settling accuracy withing 70 ps. Extra scaling capacitors in the SCA enable SAR reference voltage levels near the supply rails, significantly reducing the SCA switch sizes. The necessity of a comparator latch reset phase is eliminated at the cost of higher comparator power consumption by the adoption of a loop-unrolled comparator improving the SAR loop timing. Top-plate charge kickback into the input buffer, a challenge that occurs within TI ADCs, is largely eliminated by implementing an additional reset phase within the SAR algorithm and the use of a boosted input T-switch. SCA and time-interleaved channel mismatch effects are addressed by calibrating each sub-ADC to an extra reference-ADC. The industry grade ADC design, achieves a spurious free dynamic range (SFDR) of 72 dB and signal to noise and distortion ratio (SNDR) of 54 dB across the entire 4 GHz frequency range. Designed in a 28 nm CMOS process, each sub-ADC consumes 33 mW from 1.8 V and 1V. The input buffer frontend uses supply voltages of 2.5 V and -1.3 V. The overall power consumption of the overall TI ADC is 3 W.

This paper presents a wideband 12 Bit 8 GS/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC), featuring a sub-2 radix architecture with an overrange of 10% and randomized sampling with mismatch correction in a 28 nm CMOS technology. For this purpose, 18 500 MHz SAR-ADCs plus an additional reference ADC are interleaved. This topology enables a randomization approach, reducing mismatch related interleaving spurs. Furthermore, the additional reference ADC operating in parallel to the main ADC enables adaptive digital calibration to correct for static and time-interleaved mismatch effects. A wideband front-end features two subsequent push-pull buffer stages to achieve a high track- and-hold (T/H) bandwidth and high sampling linearity, while improving kickback related settling limitations. After calibration, the ADC achieves a signal to noise and distortion ratio (SNDR) of 56.8 dB and a spurious free dynamic range (SFDR) of 80 dBc applying a single full scale sine wave tone close to the Nyquist frequency of 4 GHz.