With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06×/ 1.08×/ 1.36× shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03×/ 1.09×/ 1.12×/ 1.15×/ 1.17× shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33×/ 1.6×/ 2.4× higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13×/ 1.32×/ 1.37×/ 1.42×/ 1.5× higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31×/ 2.42×/ 2.55×/ 3.04× lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD= 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time (TRA), and write access time (TWA) are also presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in TRAcompared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in TWAcompared to D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows 2.33x narrower spread in hold power @ VDD= 0.4 V compared to D6T SRAM cell.