This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.

Switch-level simulation has become a common means of validating the behavior of MOS circuits. In this paper, we present a new cache-based simulation method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory, the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables, and significantly reduce the memory requirements.>

Methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model are presented. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a single fully integrated capture-compile-simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit.>

Article Free Access Share on Accelerating switch-level simulation by function caching Author: Larry G. Jones Department of Computer Science, University of Illinois at Urbana-Champaign Department of Computer Science, University of Illinois at Urbana-ChampaignView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 211–214https://doi.org/10.1145/127601.127666Published:01 June 1991Publication History 4citation134DownloadsMetricsTotal Citations4Total Downloads134Last 12 Months4Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Fast batch and incremental algorithms for creating and updating the netlist underlying a hierarchical schematic design are presented. The algorithms can be used either for maintaining the netlist as a data structure for further online processing or as a file for use with other offline design tools that are downstream from the compilation process. The batch algorithm uses a preorder traversal of the design hierarchy to derive the netlist. The incremental algorithm trims this traversal to only those paths leading to changes in the netlist. For most user modifications the netlist can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user.>

We present efficient algorithms for exhaustive and incremental evaluation of circular attributes under any conditions that guarantee finite convergence. The algorithms are derived from those for noncircular attribute grammars by partitioning the underlying attribute dependency graph into its strongly connected components and by ordering the evaluations to follow a topological sort of the resulting directed acyclic graph. The algorithms are efficient in the sense that their worst-case running time is proportional to the cost of computing the fixed points of only those strongly connected components containing affected attributes or attributes directly dependent on affected attributes. When the attribute grammar is noncircular or the specific dependency graph under consideration is acyclic, both algorithms reduce to the standard optimal algorithms for noncircular attribute evaluation.

We present fast techniques for creating the netlist underlying a hierarchical schematic design. The methods can be used either for creating the netlist as a data structure for further online processing or for creating the netlist as a file for use with other offline design tools that are downstream from the compilation process. The methods we present have been used successfully in the implementation of a hierarchical schematic capture system that supports both netlist compilation and switch-level logic simulation.

Fast incremental techniques for maintaining and quickly updating the net list underlying a hierarchical schematic design are presented. For most user modifications the net list can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user. As a side result, the incremental net list compiler yields a list of affected electrical nodes that can be used to guide an incremental simulator which resimulates only the affected region of the circuit.>

The attribute grammar technique used for design of structure editors is suggested as a foundation for building hierarchical incremental design editors for VLSI circuits. The usual definition of attribute grammars is extended: the cycles that occur in VLSI design make us come to terms with circular attributes (under conditions that guarantee their least fixpoint solution, namely that the functions be monotone and yield values over a lattice of bounded height). Many interesting VLSI design problems can be cast in attributes meeting this condition, for example, timing verification, logic simulation, power dissipation, and adherence to clocking disciplines, to name a few. As an illustration of the formalism, attributes are presented which solve the All Bidirectional Edges problem that labels the direction of information flow in a circuit. The incremental evaluation algorithm of [Rep82] is extended to handle fixpoint computations of circular attributes by noting that when the dependency graph is broken into its strongly connected components, a directed acyclic graph results. The worst-case running time of the resulting incremental evaluation algorithm is bounded by O (hk |AFFECTEDSCC|), where h is the height of the largest attribute lattice, k the largest number of attributes in any one strongly connected component, and |AFFECTEDSCC| the number of strongly connected components affected by a single modification to the design tree.