Increasing complexity of microprocessor-based systems puts pressure on a product's time-to-market.We describe a methodology used in designing the system interface of UltraSPARC-I.This methodology allowed us to define the system interface architecture, verify the functionality, perform timing and noise analysis and do the physical board design in parallel.This concurrency permitted rapid implementation of the microprocessor and the system.

A formal verification method for concurrent systems is presented. The technique shows a correspondence between automata representing an implementation and specification behavior. The correspondence is called a refinement relation, and is particularly well-suited for theorem-provers. Since the method does not rely on enumerating all the states, it can be applied to systems with an infinite or unknown number of states. This substantially expands the class of hardware designs that can be formally verified. The method is illustrated by proving the consistency of a concurrent, non-deterministic model of cache memory. The proof is carried out using the HOL (higher-order logic) theorem-prover.>

A description is given of the formalization of some state-machine theory in a higher-order logic (HOL) theorem prover and the results obtained applying that theory. It is shown that by building state-machine theory in HOL, the verification of state-machines is rendered much more tractable. This is illustrated using a family of redundantly encoded serial-parallel multipliers.>

This paper describes an LSI data stream processor that has been optimised for filtering algorithms. Its novel serial architecture achieves high throughput by performing many operations concurrently, and permits long data wordlengths in a compact NMOS implementation. The instruction set supports recursive and nonrecursive filters and a variety of nonlinear signal processing functions.

Independently of the method of demodulation, the time quantisation of a pulse frequency modulated signal causes an error proportional to the demodulator bandwidth, to the time quantisation interval, and to the ratio of the modulation frequency to the modulation frequency range. The necessity of having a very short quantisation interval leads to a very high effective input sampling rate to a digital demodulator. This high effective sampling rate, together with large time constants needed to demodulate the signal, precludes the use of a conventional digital filter. It is possible, however, to take advantage of the special form of the demodulator input signal to design a computationally efficient state-space filter.