Demo Data from EDBT 2026 / reviewers in the wild / expert
Corinna Lee
dblp:24/1846
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Integrated circuit design · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic |
0.0 | 1 | 1989 | Multistep Gradual Rounding · IEEE Trans. Computers 1989 |
Integrated circuit design › digital arithmetic circuits › floating-point unit design
rounding |
0.0 | 1 | 1989 | Multistep Gradual Rounding · IEEE Trans. Computers 1989 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Multistep Gradual RoundingabstractA value V is to be rounded to an arbitrary precision resulting in the value V". Conventional rounding technique uses one step to accomplish this. Multistep rounding uses several steps to round the value V to successively shorter precisions with the final rounding step producing the desired value V". This alternate rounding method is one way to implement with the minimum of hardware, the denormalization process that the IEEE Floating-Point Standard 754 requires when underflow occurs. There are certain cases for which multistep rounding produces a different result than single-step rounding. To prevent such a step error, the author introduces a rounding procedure called gradual rounding that is very similar to conventional rounding with the addition of two tag bits associated with each floating-point register.> Corinna Lee |
IEEE Trans. Computers | 1 |