In this paper we present a new formal model, called p-FSM, for system-level power management design. The p-FSM is a modular, compositional, hierarchical, and unified model for hardware and software components. The model encapsulates power management control mechanisms, operating states and properties of a component that affect power, energy and thermal aspects of the system. Inter-component dependencies are modeled through a component-based interface. By connecting multiple p-FSMs we gradually compose the model of the whole system which ensures correct-by-construction system-level control sequencing. The model can also be used to formally verify the functional correctness of the power management design.

We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with other hardware and software components.A common approach to the modeling of processors for HW/SW co-verification relies on instruction-accurate ISA models combined (i.e.wrapped) with the bus interface models (BIM) that generate the clock/phase-accurate timing at the component's interface pins.However, for DSPs and new microprocessors with complex architectural features this approach is from our perspective not acceptable.The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them.We therefore propose an alternative approach in which the processor ISAs themselves are modeled in a full cycle/phase-accurate fashion.The bus interface model is then reduced to just modeling the connection to the pins.Our models have been integrated into a number of cycle-based and event-driven system simulation environments.We present one such experience in incorporating these models into a VHDL environment.The accuracy has been verified cycle-by-cycle against the gate/RTL level models.Multiprocessor debugging and observability into the precise cycleaccurate processor state is provided.The use of co-verification models in place of the RTL resulted in system speedups up to 10 times, with the cycle-accurate ISA models themselves reaching performances of up to 123K cycles/sec.

This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation description, the architectural details and pipeline operations of modern DSP processors can be covered. Beyond the behavioral model, LISA descriptions include other architecture-related information like the instruction set. The information provided by LISA models enables automatic generation of simulators and assemblers which are essential elements of DSP software development environments. In order to proof the applicability of our approach, a realized model of the Texas Instruments TMS320C6201 DSP is presented and derived LISA code examples are given.

In this survey, key drivers in design methodology are provided that enable successful design of systems-on-a-chip for the highly competitive telecommunications market. Main components of a design environment are described that fulfill the requirements of today's system design: efficient verification by means of fast simulation, integration of intellectual property, support of HW/SW co-design by means of a generic machine description language, generation of dedicated hardware blocks for high speed applications, and the link from system level performance evaluation to implementations in hardware and software.

Multirate Dataflow Graphs (MR-DFGs) are used for modelling iterative computations, allowing concurrency and arbitrary data rates at ports. This model is often used for signal processing algorithms. For static scheduling the iteration period bound represents the final barrier for the computation speed, the approximation of which is often the goal of an implementation. For the singlerate case (SR-DFG), where all rates are one, an explicit bound exists and is subject of many published papers. This work presents a bound for the multirate case, which reduces to the known bound if applied to an SR-DFG. Assumptions made are a vectorized execution and a blocked schedule that organizes multiple iterations inside one period (also called execution cycle). The influence of characteristic properties in the multirate case is emphasized and related to terms from the Petri-Nets theory.

Digital Signal Processors (DSPs) have become key components for the implementation of digital signal processing systems. With DSPs moving into new application domains and the increasing complexity of modern DSP architectures, efficient programming support receives major interest. Therefore, an optimizing compiler becomes a must for future DSP-architectures. Todays DSP compilers result in significant overheads both in memory consumption and program execution time compared to hand-written assembly code. This is mainly due to an inefficient compiler support of the DSP specific architectural features, such as the modulo-addressing capability which is an enabling feature for a large class of DSP algorithms. Within this paper we analyze why existing compilers fail short in supporting the modulo-addressing mode and present a compiler concept that allows the efficient utilization of this feature. We describe how an advanced compiler optimization strategy allows a near optimum support of the modulo-addressing mode, and point out why this concept is favorable to DSP-specific language extensions.

Minimizing the Fisher information measure over the set of power spectrum densities fitting a finite number of autocorrelation lag constraints is treated. Due to an explicit control of the derivative values of the densities, the Fisher information measure produces a useful smoothing effect. The Fisher information based estimate exhibits improved characteristics compared to the maximum entropy approach proposed by Burg (1967). We show that the resulting power spectrum estimate is positive, and along with the autocorrelation constraints, satisfies a generalized Riccati differential equation. In general, the true estimate of the power spectrum may be obtained only by numerically integrating the corresponding boundary value problem. For real time applications, we therefore propose a fast and numerically stable approximate solution in explicit trigonometric form. Although suboptimal, the proposed approach has proven to be advantageous especially for flat spectra. The presented theory is verified on simulated examples.

This paper presents a technique for simulating processors and attached hardware using the principle of compiled simulation. Unlike existing, inhouse and off-the-shelf hardware/software co-simulators, which use interpretive processor simulation, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. In this paper, the sources of the speedup and the limitations of the technique are analyzed and the realization of the simulation compiler is presented.

DSP algorithms are frequently represented by dataflow graphs. These graphs serve as an abstract input specification for an implementation, either in software or hardware. While doing so, the transformation process might require a special treatment of specific subgraphs within the complete dataflow graph. A hierarchization of a subgraph appears as a replacement of the subgraph by a single vertex, representing the same functionality. The subgraph to be hierarchized might be defined by the designer manually or identified automatically, matching certain criterions. Because of the possibility of introducing a deadlock, not every hierarchization is valid. This paper presents an approach that allows to identity such deadlocking subgraphs. If an a priori defined subgraph is identified to result in a deadlock, a concept is presented that allows one to separate the subgraph into sub-subgraphs of maximum size. This allows to apply the special treatment to these sub-subgraphs and not to cancel it completely.

The retiming of DSP algorithms exhibiting multirate behavior is treated. Using the non-ordinary marked graph model and the reachability theory, we provide a new condition for valid retiming of multirate graphs. We show that for a graph with n nodes the reachability condition can be split into the reachability condition for the topologically-equivalent unit-rate graph (all rates set to one), and (n/sup 2/-n)/2 rate-dependent conditions. Using this property a class of equivalent graphs of reduced complexity is introduced which are equivalent in terms of retiming. Additionally, the circuit-based necessary condition for valid retiming of multirate graphs is extended for the sufficient part.

Vectorization of digital signal processing programs given in form of data-flow graphs (DFG) is treated. It is shown that for cyclic unit-rate graphs an inherent upper bound on the linear vectorization factor exists. Using the retiming transformation of the original graph this bound can be raised up to a transformation-independent bound which is in general not tight. The authors give a sufficient condition for efficient linear vectorization (vectorization approaching the bound) and propose a corresponding algorithm. As a side result, a useful theorem for retiming of strongly connected graphs is given.>

A synthesis environment that targets software programmable architectures such as digital signal processors (DSPs) is presented. These processors are well suited for implementation of real-time signal processing systems with medium throughput requirements. Techniques that tightly couple the synthesis environment to an existing communication system simulator are also presented. This enables a seamless transition between the simulation and implementation design level of communication systems. Special focus is on optimization techniques for mapping data flow oriented block diagrams onto DSPs. The combination of different mapping and optimization strategies allows comfortable synthesis of real-time code that is highly adapted to application-specific needs imposed by constraints on memory space, sampling rate, or latency. Thus, tradeoff analysis is supported by efficient interactive or automatic exploration of the design space. All presented concepts are illustrated by the design of a phase synchronizer with automatic gain control on a floating-point DSP.>