In some modern FPGAs and CPLDs, PLA(programmable logic array)-style logic blocks can be used as the storage elements for improved logic density and performance. PLA-style logic blocks were originally deployed in the early PLDs. Due to recent research developments in the FPGA community such as [6] and [4], PLA-style logic blocks are becoming an effective storage alternative in FPGAs. This paper presents an approach with clustering and functional decomposition to implement the circuits using the minimum number of PLA-style logic blocks. One important feature is that it simultaneously considers the routing resource reduction for better circuit performance after place-and-route. In order to effectively use PLA-style logic blocks in large clusters, functional decompositions are used to decompose large clusters so that the encoding functions and base functions can be mapped into PLA-blocks. Furthermore, implicit representation[5] of the crucial steps in the functional decomposition is used to consider 1) number of inputs, 2) number of product terms. 3) number of outputs required for the PLA-block synthesis. We have developed an algorithm called PLA_SynT that can be used in the logic synthesis flow for CPLDs and FPGAs with PLA-blocks. MCNC benchmarks are used to test PLA_SynT and the experimental results are compared with TEMPLA[1]. PLA_SynT shows 10.24% improvement over TEMPLA[1], in terms of the number of PLA-blocks needed to implement the circuit. PLA_SynT also shows 14.41% improvement over EMB_Syn[3] in circuit performances while maintaining comparable circuit areas.

Embedded memory blocks (EMBs) are used in modern field programmable gate arrays (FPGAs) for implementation of on-chip memories or specialized logic functions[1]. In this paper, we propose an integrated approach with structural clustering and functional decomposition to minimize the circuit area using EMBs while preserving the circuit delay. The structural clustering method is based on the concepts of Maximum Fanout Free Cone (MFFC)[5] and Maximum Fanout Free Subgraph (MFFS)[5]. In order to effectively use EMB in large clusters, single-output and multiple-output functional decompositions are used to decompose large clusters so that the encoding functions or base functions can be implemented by EMBs. It also considers multiple EMBs for individual large cluster so that better area reduction can be obtained. We have developed an algorithm called EMB_Syn that can be used as a postprocessing tool in the FPGA synthesis flow. MCNC benchmarks are used to test EMB_Syn on Altera's FLEX10K device family and the experimental results are compared with those by EMB_Pack[8] and SMAP[10]. When EMB_Syn is used as postmapping processing, it shows 45.06% and up to 5.23% improvements over EMB_Pack and SMAP, respectively, in terms of the covered area by EMBs.

The "quadratic placement" methodology is rooted in [Module Placement Based on Resistive Network Optimization, Proud: A Sea-Of-Gate Placement Algorithm, A Combined Force and Cut Algorithm for Hierarchical VLSI Layout]and is reputedly used in many commercial and in-house tools forplacement of standard-cell and gate-array designs. The methodologyiterates between two basic steps: solving sparse systems oflinear equations, and repartitioning. This work dissects the implementationand motivations for quadratic placement. We firstshow that (i) Krylov subspace engines for solving sparse systemsof linear equations are more effective than the traditional successiveover-relaxation (SOR) engine [A Unified Approach to Partitioning and Placement] and (ii) order convergence criteriacan maintain solution quality while using substantially fewersolver iterations. We then discuss the motivations and relevanceof the quadratic placement approach, in the context of past and futurealgorithmic technology, performance requirements, and designmethodology. We provide evidence that the use of numerical linearsystems solvers with quadratic wirelength objective may be due tothe pre-1990's weakness of min-cut partitioners, i.e., numerical engineswere needed to provide helpful hints to min-cut partitioners.Finally, we note emerging methodology drivers in deep-submicrondesign that may require new placement approaches to the placement problem.

Article Faster minimization of linear wirelength for global placement Share on Authors: Charles J. Alpert IBM Austin Research Laboratory, Austin, TX IBM Austin Research Laboratory, Austin, TXView Profile , Tony F. Chan UCLA Mathematics Department, Los Angeles, CA UCLA Mathematics Department, Los Angeles, CAView Profile , Dennis J.-H. Huang UCLA Computer Science Department, Los Angeles, CA UCLA Computer Science Department, Los Angeles, CAView Profile , Andrew B. Kahng UCLA Computer Science Department, Los Angeles, CA and Cadence Design Systems, Inc., San Jose, CA UCLA Computer Science Department, Los Angeles, CA and Cadence Design Systems, Inc., San Jose, CAView Profile , Igor L. Markov UCLA Mathematics Department, Los Angeles, CA UCLA Mathematics Department, Los Angeles, CAView Profile , Pep Mulet UCLA Mathematics Department, Los Angeles, CA UCLA Mathematics Department, Los Angeles, CAView Profile , Kenneth Yan UCLA Computer Science Department, Los Angeles, CA UCLA Computer Science Department, Los Angeles, CAView Profile Authors Info & Claims ISPD '97: Proceedings of the 1997 international symposium on Physical designApril 1997 Pages 4–11https://doi.org/10.1145/267665.267670Online:01 April 1997Publication History 17citation150DownloadsMetricsTotal Citations17Total Downloads150Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access