A logic diagnosis procedure produces a set of can-didate faults that are expected to identify the defects present in a faulty chip. To reduce the number of candidates produced, diagnostic tests are often needed. The use of diagnostic tests increases the storage requirements of a test set. Earlier works reduced the input storage requirements of a fault detection test set by using each stored test to apply several different tests. When applied to diagnostic tests, the tests were selected by performing diagnostic fault simulation of a basic fault model. In this paper, we apply this approach to target large sets of candidate faults produced by a logic diagnosis tool. A procedure for the selection of a subset of the available tests to be used as diagnostic tests is described. Experimental results for simulated defects in benchmark circuits and the logic blocks of an OpenSPARC T1 microprocessor show that the diagnostic test set selected using our approach produces better diagnosis results, with a minimal increase in input storage, compared to a diagnostic test set produced by a commercial tool.

Fail data is collected by a tester from faulty units to allow defect diagnosis to be carried out. The fail data describes the full output response of the unit. The volume of fail data that faulty units produce during volume diagnosis can exceed the tester memory capacity. Existing solutions stop the fail data collection for a faulty unit after sufficient fail data has been collected or modify the test set to produce less fail data. This article considers the format for storing fail data on the tester. This article suggests a hybrid approach, where full output responses are stored for some tests, and only pass/fail information is stored for the remaining tests. This article describes procedures based on diagnostic fault simulation to determine a subset of tests for which full output responses are needed and for adding new tests such that fewer tests in the extended test set would require full output responses. The experimental results for benchmark circuits demonstrate the reductions in fail data volume that can be achieved by a hybrid approach.

Yield improvement requires information about the defects present in faulty units. This information is derived by applying a logic diagnosis procedure to the fail data collected by a tester from faulty units. It is typical in the early stages of yield learning to find faulty units that produce excessive volumes of fail data. The current practice is to terminate the fail data collection and possibly discard the fail data already collected for the unit. An earlier study shows that a faulty unit may produce excessive volumes of fail data for some tests but not for others. Based on this observation, a possible solution is to collect full fail data only for tests where this is feasible and pass/fail information for other tests. For this approach to be practical, it is necessary to be able to perform logic diagnosis with hybrid fail data that consists of full fail data for some tests and only pass/fail information for other tests. The main challenge in designing such a procedure is to balance the use of the two types of data to produce accurate logic diagnosis results. This article describes a logic diagnosis procedure, from the class of procedures used by commercial tools, that addresses this challenge. Experimental results for benchmark circuits demonstrate the importance of pass/fail information in this scenario.

A test reordering algorithm is presented to improve the results of scan chain diagnosis when a limited amount of fail data is collected by the tester. Tests are reordered based on information derived by applying an enhanced defect diagnosis procedure to the faulty units with scan defects. Tests that are found important for diagnosis of more faulty units are placed earlier in the test set based on the expectation that these tests will be useful for diagnosis of other faulty units as well. Experimental results collected for benchmark circuits in the presence of single and multiple scan chain defects indicate that reordering tests based on diagnostic information improves the quality of scan chain diagnosis when a limited amount of fail data is collected by the tester.

As part of a yield improvement process, fail data is collected from faulty units. Several approaches exist for reducing the tester time and the volume of fail data that needs to be collected based on the observation that a subset of the fail data is sufficient for accurate defect diagnosis. This article addresses the volume of fail data by considering the test set that is used for collecting fail data. It observes that certain faults from a set of target faults produce significantly larger numbers of faulty output values (and therefore significantly larger volumes of fail data) than other faults under a given test set. Based on this observation, it describes a procedure for modifying the test set to reduce the maximum number of faulty output values that a target fault produces. When defects are considered in a simulation experiment, and a defect diagnosis procedure is applied to the fail data that they produce, two effects are observed: the maximum and average numbers of faulty output values per defect are reduced significantly with the modified test set, and the quality of diagnosis is similar or even improved with the modified test set.

During fail data collection, a tester collects information that is useful for defect diagnosis. If fail data collection can be terminated early, the tester time as well as the volume of fail data will be reduced. Test reordering can enhance the ability to terminate the process early without affecting the quality of diagnosis. In this paper, test reordering targets logic defects based on information that is derived during defect diagnosis. The defect diagnosis procedure is enhanced to identify tests that are useful for defect diagnosis across a sample of faulty instances of a circuit. Tests that are determined to be useful for more faulty instances of a circuit are placed earlier in the test set based on the expectation that the same tests will be useful for other faulty instances of the circuit. The experimental results for logic defects in benchmark circuits support the effectiveness of this approach and indicate that test reordering helps to terminate fail data collection early without impacting the diagnosis quality.

A complete industrial defect diagnosis flow for yield learning includes the use of diagnostic tests. Diagnostic tests improve the ability of a defect diagnosis procedure to provide accurate diagnosis results. Because of the costs involved, diagnostic test generation is carried out only for units where the results of defect diagnosis based on a fault detection test set are not accurate enough. This paper formulates the diagnostic test generation problem under this scenario with the goal of simplifying the test application process for diagnostic tests, taking into consideration that different units require different diagnostic tests. The parameters that the problem formulation targets are the numbers of diagnostic tests for the individual units, and the total number of diagnostic tests for all the units. A lower total number of diagnostic tests increases the similarity between the diagnostic test sets for the individual units. With similar diagnostic test sets, the units are partitioned into groups such that all the units in a group are tested using the same diagnostic test set. The paper describes a diagnostic test generation procedure that uses dynamic test compaction to optimize these parameters.

Faster failure isolation is critical for manufacturing yield ramp and product time to market. Higher diagnosis resolution is essential for faster defect isolation and root-cause identification. A detection oriented test set is targeted for fault coverage and does not provide maximum diagnostic resolution. In this paper, we present the design and architecture of a state of the art diagnostic ATPG tool for industrial-scale designs. We develop a novel diagnostic test generation methodology which first generates deterministic diagnostic test content to distinguish the diagnosis suspects. If tester memory is available then additional N-detect oriented tests are generated to augment the content. Further, we present techniques to improve performance of diagnostic fault simulation for industrial-scale designs. Experimental results on Intel® Core™ microprocessor designs indicate 3X-114X speed up with up-to 2X memory overhead. Silicon failure data collected on sort wafer fails showed the effectiveness of the hybrid diagnostic content in improving the diagnostic resolution by 2.8x to 3X when compared with content generated from an industry standard diagnostic test generator. Silicon results are evaluated on Intel® Core™ microprocessor.

An accurate and high-resolution diagnosis enables physical failure analysis (PFA) to identify and understand the root-cause of integrated-circuit failure. Despite many existing techniques for improving diagnosis, resolution is still far from ideal, which hinders PFA and other analyses. To address this challenge, we extend the capability of PADRE (physically-aware diagnostic resolution enhancement), a powerful machine learning based diagnosis resolution improvement technique, with a novel, active learning (AL) based PFA selection approach. An active-learning based PADRE (AL PADRE) selects the most useful defects for PFA in order to improve diagnostic resolution. AL PADRE provides an alternative to the normal PFA selection procedure, it improves the the accuracy of PADRE, and thus enables a more accurately improved resolution. AL PADRE is validated by both simulation-based experiment and silicon experiment. Simulation-based experiments show that by using AL PADRE, the number of PFAs required for increasing the accuracy to a stable level of 90% is reduced by more than 60% on average compared to baseline approach, and AL PADRE consistently outperforms the baseline approach for accuracy improvement in various scenarios. In the silicon experiment, by using AL PADRE, the number of chips needed to undergo PFA was reduced by more than 6x in order to increase diagnosis accuracy by more than 20%.

This paper presents an algorithm for reducing the test data volume collected by a tester for defect diagnosis of an IC and the tester time. The tester executes the tests and transfers the failing test responses one by one from the tester capture memory to the tester data-logs. While the tester is transferring the fail data, the proposed algorithm analyzes the failing outputs for every test and determines if the test is a potential contributor to the identification of defects. If not, then the test is eliminated from the tester data-logs. Otherwise, the test may replace an existing test or be added as a new test. The addition and replacement of tests continue until the algorithm determines that the fail data transferred to the tester data-logs is sufficient for accurate defect diagnosis. The early termination of the fail data transfer reduces the overall tester time. The effectiveness of the method was verified using real defects in industry fabricated dies. The algorithm was also implemented in a test program library and integrated into a production fail flow for sort data-log optimization. The overhead of the algorithm was minimal, and yielded a 5x reduction in the test data trasfer time.

With the increasing transistor count and design complexity of modern integrated circuits, a large volume of fail data is collected by the tester for a failing die. This fail data is analyzed by a diagnosis procedure to obtain information about the defects in the die that caused it to fail. However, large portions of the fail data are not necessary for diagnosis. As a result, the diagnosis procedure spends time analyzing unnecessary data, thus decreasing its speed and throughput. We present a methodology to minimize the amount of fail data that is provided to the diagnosis procedure without compromising the diagnosis accuracy (DA). Our methodology evaluates the outputs at which the tests failed to eliminate noncontributing failing tests. The efficacy of our algorithm is demonstrated using fail data from industry fabricated chips. The experimental results show that, on average, our algorithm achieves fail data minimization of 40% while maintaining an average DA of 95%. The speed of the diagnosis procedure is increased by 39%.

This talk focuses on test and debug challenges that are unique to large die products. A technical review of problems being faced today specific to test quality, test time, test cost, electrical and speed content, and debug will be outlined along with some current solutions being pursued to drive large die products to production quality. The talk concludes with a discussion about new solutions and areas of innovation that will be necessary to keep future generations of these products manufacturable, and on a cadence that meets the stringent time to market requirements.

This paper describes a method for built-in generation of functional broadside tests for a circuit that is embedded in a larger design, taking functional constraints on its primary input sequences into account. The constraints are captured by functional input sequences of the design. Specifically, the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.

Post silicon speed-path debug and production volume diagnosis for yield learning are critical to meet product time to market demand. In this paper, we present Logic BIST speed-path debug technique and methodology for achieving higher frequency demand. We have developed a methodology for Logic BIST production fail volume diagnosis and presented tester time and memory overhead tradeoffs and optimization for enabling volume diagnosis. Results are presented showing successful isolation of silicon speed-paths on Intel® SOCs.

Following design-for-manufacturability (DFM) guidelines during chip design can lower the possibility of occurrence of systematic defects. In this paper, we investigate the use of DFM guidelines during the defect diagnosis process with the goal of identifying which DFM guidelines are responsible for the defects present in failing chips. We also introduce a new metric called diagnostic coefficient that allows us to rank the guidelines according to their contribution of hard-to-diagnose defects. DFM guidelines that are ranked high should be applied during chip design in order to obtain chips that are easier to diagnose.

Diagnosis of functional failures can be used to debug design issues, isolate manufacturing defects, and improve manufacturing yield. Automated failure analysis and rapid root-cause isolation is critical for meeting ever decreasing product time to market demand. Conventional debug approach requires in-depth architecture knowledge and debug expertise. In this paper, we present a two phase approach for isolating microprocessor functional failures. First, failing functional blocks are identified utilizing functional fault simulation. Then, algorithmic diagnosis techniques are applied to accurately identify the failing signals within a functional block. Results are presented showing successful isolation of silicon defects on Intel® Core¿dual-core processor.

A methodology using design-for-manufacturability (DFM) layout guidelines as a basis for modeling and detecting systematic defects was proposed earlier. In this paper, we show that this methodology can be extended to prioritize layout locations according to the importance of applying DFM guidelines to them. Prioritization is done based on test considerations including coverage and test set size. In particular, this methodology can identify layout locations where failure to follow a DFM guideline may result in test holes due to hard-to-detect defects. The prioritized list can be used by layout tools to create circuits that are easier to test.

With shrinking feature sizes of manufacturing processes, the occurrence of systematic defects is expected to increase. In this paper, we present techniques for identifying potential systematic defect candidates from design-for-manufacturing (DFM) layout guidelines. DFM guidelines are tightened to find layout locations as potential sites for systematic defects, affected transistors are identified at the schematic level, and defect behaviors are translated to gate level logic faults. Experimental results are presented on an Intel Pentiumê4 design for the evaluation of existing tests in screening systematic failures and identifying potential test holes. Additional test content is generated for improving test quality.

In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the "primary input (PI) pattern generation and simulation" step and instead employs scan-dump values extracted from the tester. We utilize backward and forward logic implications of the scan-dump values to reconstruct more logic values for the circuit signals. Furthermore, we employ the reset state for the non-scan latches of the design to increase the number of specified signals in the overall circuit. Experimental results on stuck-at faults on industrial designs show that, in most cases, these reconstructed values are sufficient to correctly diagnose a fault, thereby avoiding hours of conventional functional diagnosis runtimes.

For nanometer manufacturing fabrication process, it is critical to narrow down the defect location for successful physical failure analysis. This paper presents a mixed-level diagnosis technique, which first performs diagnosis at logic level, and then performs switch-level analysis to locate a defect at transistor level. An efficient single pass mixed-mode diagnosis flow proposed to isolate defects within a cell. Experimental results showed significant improvement in precision over traditional logic diagnosis with only a fractional increase in run-time. The proposed mixed-level diagnosis technique was applied to successfully isolate silicon defects

Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs

A procedure for using fault dominance in a large volume diagnosis environment is described. Fault dominance is shown to be useful for reducing the fault simulation time during diagnosis when used together with the concept of pattern dependence and maximally dominating faults. Results for both ISCAS benchmarks and industrial circuits are reported. The results show 9 % to 44% average reduction in the fault simulation time for these circuits

This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90 nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed.

This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs. An incremental method for test generation is presented. Metrics to evaluate the richness of the test set are presented. The natural N-detect profiles of regular one-detect test sets and the impact to test data volume and test time of generating additional patterns is studied. Results are presented on an lntel/spl reg/ Pentium/spl reg/ 4 processor. Simulation results from evaluating the patterns on layout extracted and random bridges are presented. Silicon data from production test shows the effectiveness of N-detect tests.

Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.

Efficient identification of fault equivalence relations is essential for effective diagnostic test pattern generation. In this paper, we present efficient techniques for identifying functionally equivalent faults in combinational circuits. The techniques are based on implication of faulty values, and evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Both static and dynamic methods are developed to exploit relations among inputs of dominator cones and further speed up the identification of equivalent fault pairs. Experimental results for all ISCAS'85 circuits, full scan versions of ISCAS'89 circuits, and ITC'99 circuits show that most of the equivalent fault pairs are identified. Significant reductions are obtained in the runtime needed to prove equivalence and the runtime for diagnostic test pattern generation compared to previously proposed approaches.

We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from. consideration before diagnostic ATPG starts, thus improving the efficiency of diagnostic ATPG. Experimental results are presented to demonstrate the effectiveness of the proposed theorems, which allow us to identify almost all the indistinguishable fault pairs in finite-state machine benchmarks.

A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stem-branch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for non-masking and multiple-path sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques.

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.