This paper presents a three-level output side gate driver circuit for 1 V thin-gate-oxide low-VtNMOSFET switch in a single inductor dual-output (SIDO) DC-DC converter using 28 nm FDOSI technology. The proposed three-level gate driver ensures almost full gate-to-source voltage swing for optimum device size, and also protects the thin-gate-oxide device from any possible over-voltage stress. The three-level gate driver allows the use of a thin-gate-oxide NMOSFET device at the output of a SIDO converter, resulting in almost three times reduction in combined switching and driver losses compared to a thick-gate-oxide NMOSFET switch. The proposed three-level gate driver and thin-gate-oxide NMOSFET offer almost 26% lesser silicon area compared to a conventional thick-gate-oxide NMOSFET device with a two-level gate driver.

Small-signal-based current mode control (CMC) and voltage mode control (VMC) design approaches are principally dominant in the existing commercial products on buck converter-based LED drivers for automotive applications. However, the control bandwidth (BW) in VMC is limited for a larger duty ratio variation, while in CMC, the over-compensating ramp may degrade the control BW, penalizing the transient performance. Load-insensitive PID controller tuning in VMC provides enhanced load transient performance, however, beyond the control BW, model validity remains a concern due to low-valued output capacitance. This paper presents small-signal-based state feedback (SF) design approach to achieve nearoptimal recovery during load transients without any load feedforward, even for a higher BW. Thereafter, SF-based multi-mode control strategy with smooth controller transition is identified to provide inherent current-loop stability along with superior light-load efficiency. Simulation results are presented to show the performance improvement using the proposed design approach.

The existence of a right-half-plane (RHP) zero in the control-to-output transfer function of a CCM (continuous conduction mode) boost converter significantly restricts the achievable control bandwidth ω c under high load current and/or voltage gain conditions when the RHP zero comes closer to the imaginary axis of the complex ‘s’ plane. Current mode control (CMC) offers superior bandwidth over voltage mode control; however, ω c is still restricted to ω rhp /3 while designing a type-II voltage compensator using an output feedback (OF) design approach. A higher ω c results in a poor phase margin, resulting in a higher voltage overshoot during a step-up reference transient. The scenario becomes more severe under digital CMC (DCMC) due to the sampling delay which further degrades the phase margin. This paper proposes a discrete-time state feedback (SF) design approach in a DCMC architecture, which significantly improve the transient performance. Using a discrete-time modeling framework, closed-loop stability analysis and controller design are carried out using both the OF and SF design approaches. Thereafter, comparative simulation case studies are shown to demonstrate the superiority of using the SF approach over the OF solution. Experimental results are presented for a synchronous boost converter with 500 kHz switching frequency.

Digital current mode control (CMC) architectures have been gaining popularity in multiphase DC-DC converters for high-current low-voltage applications, in which a configurable digital platform enables one to achieve (i) effective phase current balancing and ripple minimization with reduced output capacitance and better thermal distribution, (ii) high efficiency by dynamic phase shading, and (iii) fast transient performance by online controller tuning. In fully digital CMC (DCMC), the phase currents are sampled once per switching cycle, and the current ripples are emulated inside the digital platform, thereby reducing ADC sampling requirement. In DCMC, the current samples can be made insensitive to switching noise, and the emulated ripple can be made insensitive to variations in phase inductances. However, one cycle delay significantly degrades cycle-by-cycle stability boundary with limited closed-loop bandwidth. This paper proposes an event-based sampling method in fixed-frequency DCMC in a multi-phase buck converter. Stability boundaries are formulated, discrete-time large-signal model is derived for stability analysis and controller design. Using mathematical analysis and simulation study, the proposed sampling is shown to significantly enhance stability boundary and transient performance over uniform sampling.

Interactive digital control using PMBus protocol can significantly improve performance, efficiency and reliability in high frequency low voltage DC (LVDC) microgrid applications using online optimization through shared clock and data. Modeling and analysis of digitally controlled standalone DC-DC converters, considering finite sampling delays, have been well reported in the past; however, modeling and analysis of fast scale stability and performance limits, under finite sampling delay and clock shift, have not been investigated so far in digitally controlled LVDC microgrids. This paper considers an intermediate bus architecture (IBA), consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, under clock-synchronized digital current mode control (DCMC). Considering the IBA dynamics, a discrete-time (DT) framework is proposed, and DT small-signal models are derived for stability and performance analysis. It is shown that the clock shift between individual converters and the sampling delays of their corresponding digital controllers have significant impacts on the fast-scale stability of the overall IBA system, which may lead to severe fast-scale instability with complex nonlinear phenomena and resulting in much higher (inductor) current ripple and RMS quantities. Simulation case studies are presented, and the stability boundaries are found to be consistent with the analytical predictions. The proposed framework will be helpful to design stable digital control in DC microgrids.

High frequency digitally controlled DC-DC converters have become popular because of offering high performance and efficiency with reduced size and thermal overheads. The output voltage of a high frequency DC-DC converter is sampled once per switching cycle followed by using a quantizer. The effects due to finite discretization may lead to various fast-scale instabilities. This primarily leads to non-smooth bifurcation, which may not occur using analog controllers for the same operating condition. These significantly increase the root-mean-square (RMS) current, thereby degrading the efficiency and violating the ripple limits. In this paper, a hardware-enabled methodology is developed to capture noise-insensitive experimental bifurcation diagrams in a high frequency DC-DC converter. This would enable one to use system, controller, and timing parameters as different bifurcation parameters. A digitally current-mode controlled buck converter is tested with 500 kHz switching frequency. Bifurcation diagrams using the proposed tool are shown to be much more informative than using a 1 GHz oscilloscope. Further, analytical methods are provided for accurate measurement of the RMS current and power spectral density under period-1 and higher periodic orbits. The proposed tool is extended to analog controllers.

Controller tuning based on linear small-signal models often results in poor closed-loop bandwidth in a boost converter in which there exists a right-half-plane (RHP) zero. This is because of the fact that small-signal models often ignore fast switching dynamics; thus the performance improvement cannot be fully explored. This paper proposes a geometry tuning in a digitally current mode controlled multiphase boost converter operating under a fixed-frequency digital pulse-width modulator (DPWM) throughout. This achieves proximate time optimal transient recovery for load step transients using a normalized load current feedforward. The latter results in near load invariant regulation; thus, a small integral gain is sufficient for minimizing the steady state error. A GaN-based 4-phase boost converter prototype is made for 48 V rated output voltage, and the measured efficiency is found to be around 97% for the input voltage range of 12 to 36 V. Test results demonstrate nearly a ten fold improvement in the (load) transient response using the proposed tuning over a conventional linear tuning. All the digital controllers are implemented using an FPGA device.

Pulse train (PT) control improves light load efficiency of a dc-dc converter by use of high and low pulses with different frequencies. This bi-frequency operation spreads the spectrum over discrete frequencies and helps in reducing effects due to EMI. This paper proposes a reconfigurable digital PT control technique in a DCM buck converter. This enables to online configure time periods and/or widths of both high and low pulses. This can take forms of a variety of light load control techniques. Discrete-time models are derived, which take the form of 1-D discontinuous maps. Thereafter, nonlinear analysis is carried out. This allows to accurately investigate dynamics of a buck converter under PT control and also provides design guidelines for achieving improved spectrum and efficiency. The proposed control method is simple to implement and requires less hardware resources compared to existing schemes. A buck converter prototype is tested, and the proposed method is implemented using an FPGA device. The analytical framework helps in analyzing existing light load control methods.

In our earlier work, we showed that the discrete-time model of a dc-dc converter governed by a pulse skipping modulation (PSM), could be modeled as a discontinuous map, comprising either 1-D functions only or a combination of 1-D and 2-D functions. In this paper, we show that the entire map can be restricted to one dimension for a wide range of parameters. As a parameter is varied, the periodicity of the output waveform may change either monotonically or non-monotonically depending on the character of the voltage mode control loop. Although the map in the right compartment is always stable, the slope of the left compartment may be greater than one for a range of control parameters, which may lead to chaos.

This paper presents the concept of a voltage controlled pulse skipping modulation (VCPSM) in a dc-dc converter, which improves the efficiency, ripple magnitude, and transient response over a wide range of light load condition. The duty ratio of VCPSM, instead of remaining constant as in a classical PSM, is controlled using the voltage mode control with an additional input voltage feed-forward along with an adjustable voltage. Because of the synchronization with the external clock, it facilitates the design of the input filter with reduced EMI problems. The sampled data model, averaged small signal model, and average power loss model are obtained to analyze the stability, dynamic performance, and efficiency, respectively. The simulation results are presented to compare the performance of VCPSM with its classical counterpart. Because of the absence of the any current sensing circuit, VCPSM may be useful for improving light load performance of high frequency power management ICs.

A novel current mode control of tri-state boost converter is proposed, which eliminates the zero in the right- half plane and improves the dynamic performance. The tri- state boost converter contains an additional switch across the inductor. Within a clock cycle, the inductor current first rises during the on interval of the main switch, then falls during the off or capacitor charging interval, and finally remains constant during the freewheeling interval when the second switch is turned on. In the proposed controller, the peak value of the inductor current is controlled by peak current mode control whereas the freewheeling current is dependent on the reference voltage. The direct control of the inductor current results in a larger bandwidth due to the fast inner loop and thereby a superior dynamic performance is obtained. The latter is established by comparison with that of voltage mode and current mode controlled classical boost converters which suffer from the RHP zero problem, as well as with other tri-state boost converter control techniques like the constant charging interval and dual mode control.