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M. Ciapponi

dblp:24/3426 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 62% Integrated circuit design · 38%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › circuit simulation
analog and mixed-signal simulation
0.011993
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Integrated circuit design
analog and mixed-signal circuits
0.011993
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Integrated circuit design › analog and mixed-signal circuits › mixed-signal circuit design
switched-capacitor circuits
0.011993
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993

Methods — techniques the papers use, named apart from their topics

dynamic memory allocation · 0.0behavioral simulation · 0.0
YearPublicationVenuePosition
1993 TOSCA: a simulator for switched-capacitor noise-shaping A/D converters
abstract
A software tool named TOSCA (Tool for Oversampled Switched-Capacitor A/D Converter Analysis) is described. The simulator is behavioral, general purpose and fully user-friendly. Because a set of basic building blocks is available, generic switched-capacitor noise-shaping A/D converters can be analyzed simply by building netlist file. Two hierarchical levels have been considered for circuit description: block level for subcircuits like quantizers and digital filters, and component level for subcircuits like the integrators where switches, capacitors and operational amplifiers are used as building elements. The developed models allow the most relevant nonideal parameters of the components to be taken into account, and a set of postprocessing facilities allows extensive analysis of the circuits. The program is written in C language, uses dynamic memory allocation, and is very fast.>
Valentino Liberali, Victor da Fonte Dias, M. Ciapponi, Franco Maloberti
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3