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Younès Karkouri

dblp:24/3475 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault analysis
0.011994
Use of Fault Dropping for Multiple Fault Analysis · IEEE Trans. Computers 1994
Electronic design automation › hardware verification and test
fault collapsing
0.011994
Use of Fault Dropping for Multiple Fault Analysis · IEEE Trans. Computers 1994
Electronic design automation
hardware verification and test
0.011994
Use of Fault Dropping for Multiple Fault Analysis · IEEE Trans. Computers 1994
Electronic design automation › hardware verification and test › fault modeling
multiple stuck-at fault
0.011994
Use of Fault Dropping for Multiple Fault Analysis · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

fault propagation · 0.0fault dropping · 0.0
YearPublicationVenuePosition
1994 Use of Fault Dropping for Multiple Fault Analysis
abstract
A new approach to fault analysis is presented. The authors consider multiple stuck-at-0/1 faults at the gate level. First, a fault collapsing phase is applied to the network, so that equivalent faults are eliminated. During the analysis the authors consider frontier faults where there is at least a normal path from each faulty line to a primary output. It is shown that the set of frontier faults is equivalent to the set of multiple faults. Given an input vector, the authors evaluate the fault-free circuit and then propagate fault effects. Assuming that fault-free response is observed, a fault-dropping procedure is then applied to eliminate faulty conditions on lines, that are either absent or may be hidden by other faulty conditions. This method is applied to some benchmark circuits and achieves a high degree of efficiency.>
Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault
IEEE Trans. Computers1
1993 On the generation of test patterns for multiple faults
El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny
J. Electron. Test.2