Paritosh K. Pandya

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40ranked-venue papers
10as first author
6since 2021 · last 2026
0000-0001-7085-0148ORCID · corroborated

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Theory of computation · 24 · 5 first-author · 5 since 2021Software engineering, systems software and programming languages · 14 · 4 first-author · 2 since 2021Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-authorArtificial intelligence and machine learning · 1Security and privacy · 1
YearPublicationVenuePosition
2026 MightyPPL: Model Checking MITL with Past and Pnueli Modalities
abstract
Metric Interval Temporal Logic ( $$\textsf {MITL} $$ ) is a popular formalism for specifying properties of reactive systems with timing constraints. Existing approaches to using $$\textsf {MITL} $$ in verification tasks, however, have notable drawbacks: they either support only limited fragments of the logic (the future only fragment $$\textsf {MITL} [\textsf{Fut}]$$ ) or allow for only incomplete verification. This paper introduces $$\textsc {MightyPPL} $$ , a new tool for translating formulae in Metric Interval Temporal Logic with Past and Pnueli modalities ( $$\textsf {MITPPL} $$ ) over the pointwise semantics into timed automata, enabling satisfiability and model checking of this expressive specification logic over both finite and infinite timed words. $$\textsc {MightyPPL} $$ optimises performance via specialised constructions for simple cases, a novel symbolic transition encoding, and a symmetry reduction technique that yields an exponential improvement in reachable discrete states. The tool generates language-equivalent automata compatible with back-ends such as Uppaal, TChecker, and LTSmin. Our evaluation demonstrates that $$\textsc {MightyPPL} $$ significantly outperforms the state-of-the-art tool $$\textsc {MightyL} $$ on future-only fragments and across various benchmarks.
Hsi-Ming Ho, S. Krishna 0004, Khushraj Madnani, Rupak Majumdar, Paritosh K. Pandya
TACAS (1)5
2025 Expressive Equivalence Between Decidable Freeze and Metric Timed Temporal Logics
abstract
We demonstrate a surprising and first-of-its-kind expressive equivalence between decidable metric and freeze logics over timed words in pointwise semantics. Our main result states that Metric Interval Temporal Logic with future, past and Pnueli modalities, MITPPL, and full unilateral timed propositional temporal logic with both future and past temporal modalities, UPTL, have identical expressiveness. One of the highlights of this paper, which allows for this equivalence, is to prove that UPTL formulas admit monadic decomposition. Our result also implies that several decidable logics for real-time specifications, such as one-variable UPTL, unilateral MITPPL, and Q2MLO, are all expressively equivalent, and the reductions between them are effective. Hence, our result unifies the fragmented expressiveness boundary of timed temporal logics. As corollaries, we resolve the open question of the decidability for full UPTL, and the variable or clock hierarchy problem for the future fragment of UPTL.
Hsi-Ming Ho, S. Krishna 0004, Khushraj Madnani, Rupak Majumdar, Paritosh K. Pandya
CONCUR5
2023 Satisfiability Checking of Multi-Variable TPTL with Unilateral Intervals Is PSPACE-Complete
abstract
We investigate the decidability of the ${0,\infty}$ fragment of Timed Propositional Temporal Logic (TPTL). We show that the satisfiability checking of TPTL$^{0,\infty}$ is PSPACE-complete. Moreover, even its 1-variable fragment (1-TPTL$^{0,\infty}$) is strictly more expressive than Metric Interval Temporal Logic (MITL) for which satisfiability checking is EXPSPACE complete. Hence, we have a strictly more expressive logic with computationally easier satisfiability checking. To the best of our knowledge, TPTL$^{0,\infty}$ is the first multi-variable fragment of TPTL for which satisfiability checking is decidable without imposing any bounds/restrictions on the timed words (e.g. bounded variability, bounded time, etc.). The membership in PSPACE is obtained by a reduction to the emptiness checking problem for a new "non-punctual" subclass of Alternating Timed Automata with multiple clocks called Unilateral Very Weak Alternating Timed Automata (VWATA$^{0,\infty}$) which we prove to be in PSPACE. We show this by constructing a simulation equivalent non-deterministic timed automata whose number of clocks is polynomial in the size of the given VWATA$^{0,\infty}$.
S. Krishna 0004, Khushraj Madnani, Rupak Majumdar, Paritosh K. Pandya
CONCUR4
2023 From Non-punctuality to Non-adjacency: A Quest for Decidability of Timed Temporal Logics with Quantifiers
abstract
Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) are prominent real-time extensions of Linear Temporal Logic (LTL). In general, the satisfiability checking problem for these extensions is undecidable when both the future (Until, U) and the past (Since, S) modalities are used (denoted by MTL[U,S] and TPTL[U,S]). In a classical result, the satisfiability checking for Metric Interval Temporal Logic (MITL[U,S]), a non-punctual fragment of MTL[U,S], is shown to be decidable with EXPSPACE complete complexity. A straightforward adoption of non-punctuality does not recover decidability in the case of TPTL[U,S]. Hence, we propose a more refined notion called non-adjacency for TPTL[U,S] and focus on its 1-variable fragment, 1-TPTL[U,S]. We show that non-adjacent 1-TPTL[U,S] is strictly more expressive than MITL. As one of our main results, we show that the satisfiability checking problem for non-adjacent 1-TPTL[U,S] is decidable with EXPSPACE complete complexity. Our decidability proof relies on a novel technique of anchored interval word abstraction and its reduction to a non-adjacent version of the newly proposed logic called PnEMTL. We further propose an extension of MSO [<] (Monadic Second Order Logic of Orders) with Guarded Metric Quantifiers (GQMSO) and show that it characterizes the expressiveness of PnEMTL. That apart, we introduce the notion of non-adjacency in the context of GQMSO (NA-GQMSO), which is a syntactic generalization of logic Q2MLO due to Hirshfeld and Rabinovich and show the decidability of satisfiability checking for NA-GQMSO.
S. Krishna 0004, Khushraj Madnani, Manuel Mazo 0002, Paritosh K. Pandya
Formal Aspects Comput.4
2022 Specification and optimal reactive synthesis of run-time enforcement shields
Paritosh K. Pandya, Amol Wakankar
Inf. Comput.1
2021 Generalizing Non-punctuality for Timed Temporal Logic with Freeze Quantifiers
S. Krishna 0004, Khushraj Madnani, Manuel Mazo 0002, Paritosh K. Pandya
FM4
2020 Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership
Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing
Log. Methods Comput. Sci.3
2019 Logical specification and uniform synthesis of robust controllers
abstract
This paper investigates the synthesis of robust controllers from a logical specification of regular properties given in an interval temporal logic QDDC. Our specification encompasses both hard robustness and soft robustness. Here, hard robustness guarantees the invariance of commitment under relaxed (weakened) assumptions. A systematic framework for logically specifying the assumption weakening by means of a QDDC formula Rb(A), called Robustness criterion, is presented. This can be used with any user specified assumption DA to obtain a relaxed (weakened) assumption Rb(DA). A variety of robustness criteria encompassing some existing notions such as k, b resilience as well as some new notions like tolerating non-burst errors and recovery from transient errors are formulated logically. The soft robustness pertains to the ability of the controller to maintain the commitment for as many inputs as possible, irrespective of any assumption. We present a uniform method for the synthesis of a robust controller which guarantees the invariance of specified hard robustness and it optimizes the expected value of occurrence of commitment across input sequences. Through the case study of a synchronous bus arbiter, we experimentally show the impact of variety of hard robustness criteria as well as the soft robustness on the ability of the synthesized controllers to meet the commitment "as much as possible".
Paritosh K. Pandya, Amol Wakankar
MEMOCODE1
2018 Logics Meet 1-Clock Alternating Timed Automata
abstract
This paper investigates Kamp-like and Büchi-like theorems for 1-clock Alternating Timed Automata (1-ATA) and its natural subclasses. A notion of 1-ATA with loop-free-resets is defined. This automaton class is shown to be expressively equivalent to the temporal logic $\regmtl$ which is $\mathsf{MTL[F_I]}$ extended with a regular expression guarded modality. Moreover, a subclass of future timed MSO with k-variable-connectivity property is introduced as logic $\qkmso$. In a Kamp-like result, it is shown that $\regmtl$ is expressively equivalent to $\qkmso$. As our second result, we define a notion of conjunctive-disjunctive 1-clock ATA ($\wf$ 1-ATA). We show that $\wf$ 1-ATA with loop-free-resets are expressively equivalent to the sublogic $\F\regmtl$ of $\regmtl$. Moreover $\F\regmtl$ is expressively equivalent to $\qtwomso$, the two-variable connected fragment of $\qkmso$. The full class of 1-ATA is shown to be expressively equivalent to $\regmtl$ extended with fixed point operators.
S. Krishna 0004, Khushraj Madnani, Paritosh K. Pandya
CONCUR3
2018 An Algebraic Decision Procedure for Two-Variable Logic with a Between Relation
abstract
In earlier work (LICS 2016), the authors introduced two-variable first-order logic supplemented by a binary relation that allows one to say that a letter appears between two positions. We found an effective algebraic criterion that is a necessary condition for definability in this logic, and conjectured that the criterion is also sufficient, although we proved this only in the case of two-letter alphabets. Here we prove the general conjecture. The proof is quite different from the arguments in the earlier work, and required the development of novel techniques concerning factorizations of words. We extend the results to binary relations specifying that a factor appears between two positions.
Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing
CSL3
2017 Making Metric Temporal Logic Rational
abstract
We study an extension of MTL in pointwise time with regular expression guarded modality Reg_I(re) where re is a rational expression over subformulae. We study the decidability and expressiveness of this extension (MTL+Ureg+Reg), called RegMTL, as well as its fragment SfrMTL where only star-free rational expressions are allowed. Using the technique of temporal projections, we show that RegMTL has decidable satisfiability by giving an equisatisfiable reduction to MTL. We also identify a subclass MITL+UReg of RegMTL for which our equisatisfiable reduction gives rise to formulae of MITL, yielding elementary decidability. As our second main result, we show a tight automaton-logic connection between SfrMTL and partially ordered (or very weak) 1-clock alternating timed automata.
S. Krishna 0004, Khushraj Madnani, Paritosh K. Pandya
MFCS3
2017 Formalizing Timing Diagram Requirements in Discrete Duration Calculus
M. Raj Mohan, Paritosh K. Pandya, Amol Wakankar
SEFM2
2016 Metric Temporal Logic with Counting
S. Krishna 0004, Khushraj Madnani, Paritosh K. Pandya
FoSSaCS3
2016 Two-variable Logic with a Between Relation
abstract
We study an extension of FO2[<], first-order logic interpreted in finite words, in which formulas are restricted to use only two variables. We adjoin to this language two-variable atomic formulas that say, 'the letter a appears between positions x and y'. This is, in a sense, the simplest property that is not expressible using only two variables.
Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing
LICS3
2014 On Unary Fragments of MTL and TPTL over Timed Words
Khushraj Madnani, S. Krishna 0004, Paritosh K. Pandya
ICTAC3
2014 Partially Punctual Metric Temporal Logic is Decidable
abstract
Metric Temporal Logic MTL[UI, SI] is one of the most studied real time logics. It exhibits considerable diversity in expressiveness and decidability properties based on the permitted set of modalities and the nature of time interval constraints I. Henzinger et al., in their seminal paper showed that the non-punctual fragment of MTL called MITL is decidable. In this paper, we sharpen this decidability result by showing that the partially punctual fragment of MTL (denoted PMTL) is decidable over strictly monotonic finite point wise time. In this fragment, we allow either punctual future modalities, or punctual past modalities, but never both together. We give two satisfiability preserving reductions from PMTL to the decidable logic MTL[UI]. The first reduction uses simple projections, while the second reduction uses a novel technique of temporal projections with oversampling. We study the tradeoff between the two reductions: while the second reduction allows the introduction of extra action points in the underlying model, the equisatisfiable MTL[UI] formula obtained is exponentially more succinct than the one obtained via the first reduction, where no oversampling of the underlying model is needed. We also show that PMTL is strictly more expressive than the fragments MTL[UI, S] and MTL[U, SI].
Khushraj Madnani, S. Krishna 0004, Paritosh K. Pandya
TIME3
2013 Deterministic Logics for UL
Paritosh K. Pandya, Simoni S. Shah
ICTAC1
2012 The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower Bound Constraints
Paritosh K. Pandya, Simoni S. Shah
ATVA1
2011 On Expressive Powers of Timed Logics: Comparing Boundedness, Non-punctuality, and Deterministic Freezing
Paritosh K. Pandya, Simoni S. Shah
CONCUR1
2010 Around Dot Depth Two
Kamal Lodaya, Paritosh K. Pandya, Simoni S. Shah
Developments in Language Theory2
2009 Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions
P. Vijay Suman, Paritosh K. Pandya
LATA2
2008 Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
abstract
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating Timed Automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh 0002, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang
DAC6
2008 Efficient guided symbolic reachability using reachability expressions
Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya
Int. J. Softw. Tools Technol. Transf.3
2007 On Sampling Abstraction of Continuous Time Logic with Durations
Paritosh K. Pandya, S. Krishna 0004, Kuntal Loya
TACAS1
2006 Timed Modelling and Analysis in Web Service Compositions
abstract
In this paper we present an approach for modelling and analyzing time-related properties of Web service compositions defined as a set of BPEL4WS processes. We introduce a formalism, called Web service timed state transition systems (WSTTS), to capture the timed behavior of the composite Web services. We also exploit an interval temporal logic to express complex timed assumptions and requirements on the system's behavior. Building upon of this formalization, we provide techniques and tools for model checking BPEL4WS compositions against time-related requirements. We perform a preliminary experimental evaluation of our approach and tools with the help of the e-government case study.
Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore
ARES2
2006 Representation, Verification, and Computation of Timed Properties in Web
abstract
In this paper we address the problem of qualitative and quantitative analysis of timing aspects of Web service compositions defined as a set of BPEL4WS processes. We introduce a formalism, called Web service timed state transition systems (WSTTS), to capture the timed behavior of the composite Web services. We also exploit an interval temporal logic to express complex timed assumptions and requirements on the system's behavior. Building on top of this formalization, we provide techniques and tools for model-checking BPEL4WS compositions against time-related requirements. We also present a symbolic algorithm that can be used to compute duration bounds of behavioral intervals that satisfy such requirements. We perform a preliminary experimental evaluation of our approach and tools with the help of an e-Government case study
Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore
ICWS2
2006 Efficient Guided Symbolic Reachability Using Reachability Expressions
Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya
TACAS3
2005 Modal Strength Reduction in Quantified Discrete Duration Calculus
S. Krishna 0004, Paritosh K. Pandya
FSTTCS2
2005 Bounded Validity Checking of Interval Duration Logic
Babita Sharma, Paritosh K. Pandya, Supratik Chakraborty
TACAS2
2003 Digitizing Interval Duration Logic
Gaurav Chakravorty, Paritosh K. Pandya
CAV2
2001 Model Checking CTL*[DC]
Paritosh K. Pandya
TACAS1
1998 Recursive Mean-Value Calculus
Paritosh K. Pandya, Y. S. Ramakrishna
FSTTCS1
1995 Finite Divergence
Michael R. Hansen, Paritosh K. Pandya, Chaochen Zhou
Theor. Comput. Sci.2
1994 On the Computational Power of Operators in ICSP with Fairness
K. Narayan Kumar, Paritosh K. Pandya
FSTTCS2
1993 ICSP and Its Relationship with ACSP and CSP
K. Narayan Kumar, Paritosh K. Pandya
FSTTCS2
1993 Infinitary Parallelism without Unbounded Nondeterminism in CSP
K. Narayan Kumar, Paritosh K. Pandya
Acta Informatica2
1992 Reasoning Algebraically about Recursion
Paul H. B. Gardiner, Paritosh K. Pandya
Sci. Comput. Program.2
1991 P - A Logic - A Compositional Proof System for Distributed Programs
Paritosh K. Pandya, Mathai Joseph
Distributed Comput.1
1986 Finding Response Times in a Real-Time System
abstract
There are two major performance issues in a real-time system where a processor has a set of devices connected to it at different priority levels. The first is to prove whether, for a given assignment of devices to priority levels, the system can handle its peak processing load without losing any inputs from the devices. The second is to determine the response time for each device. There may be several ways of assigning the devices to priority levels so that the peak processing load is met, but only some (or perhaps none) of these ways will also meet the response-time requirements for the devices. In this paper, we define a condition that must be met to handle the peak processing load and describe how exact worst-case response times can then be found. When the condition cannot be met, we show how the addition of buffers for inputs can be useful. Finally, we discuss the use of multiple processors in systems for real-time applications.
Mathai Joseph, Paritosh K. Pandya
Comput. J.2
1986 A Structure-Directed Total Correctness Proof Rule for Recursive Procedure Calls
abstract
Recursive procedures have been extensively used for a long time, yet it was only in 1977 that Sokolowski gave a proof rule for the total correctness of recursive procedure calls. Unfortunately, even for simple programs his rule requires the use of complex predicates that encode information about the depth of recursion. Thus the rule can be very difficult to use for practical programs. In this paper we propose a new rule for this purpose. This rule makes use of the structure of the recursion which is discovered by carrying out an interval analysis of the procedure call graph in the proof. Proofs using this rule are simpler to carry out, and it is shown that Sokolowski's rule is in fact a special case of the new rule.
Paritosh K. Pandya, Mathai Joseph
Comput. J.1