This study proposes a Spread Spectrum Clock Generator (SSCG) for Serial-ATA II, which is realized by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable divider with little power consumption added. This half-integer divider utilizes a half division ration to obtain a small phase jump to reduce quantization noise. The SSCG prototype, which has been produced in 0.18-μm CMOS technology, achieves an output clock of 3 GHz and 4883ppm down spread with a 30 KHz triangular waveform. The EMI reduction is 13 dB and the power consumption is as low as 12 mW under 1.8-V power supply.

This paper proposes a low-cost high-throughput multistandard transform (MST) core, which can support MPEG-1/2/4 (8 × 8), H.264 (8 × 8, 4 × 4), and VC-1 (8 × 8, 8 × 4, 4 × 8, 4 × 4) transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. This achieves a 44.5% reduction in adders in the proposed MST, compared with the direct implementation method. With eight parallel computation paths, the proposed MST core has an eightfold operation frequency throughput rate. Measurements show that the proposed CSDA-MST core achieves a high-throughput rate of 1.28 G-pels/s, supporting the (4928 × 2048@24 Hz) digital cinema or ultrahigh resolution format. This is possible only with 30 k gate counts when implemented in a TSMC 0.18- μm CMOS process. The CSDA-MST core thus achieves a high-throughput rate supporting multistandard transformations at low cost.

In this paper, a 2-D forward discrete cosine transform (FDCT) and inverse DCT (IDCT) core are presented. The proposed DCT core uses a single 1-D transform core and a transpose memory in order to achieve an area-efficient design. By exploiting the even and odd symmetrical properties of the FDCT and IDCT computations, the DCT core can share hardware resources. Furthermore, first-dimensional (1st-D) and second-dimensional (2nd-D) operations can be run simultaneously (1st-D FDCT, 2nd-D FDCT, 1st-D IDCT, 2nd-D IDCT) in the proposed 1-D core by using the proposed time division strategy, which shares hardware resources achieving a high-throughput design. Measurement results show that the DCT core achieves a throughput of 250 MP/s when simultaneously operating FDCT and IDCT, consuming only 19650 logic gates when fabricated using the TSMC 0.18-μm CMOS process. The DCT core achieves superior hardware efficiency compared to the existing cores.

In this paper, a spatial and time scheduling strategy, called the space-time scheduling (STS) strategy, that achieves high image resolutions in real-time systems is proposed. The proposed spatial scheduling strategy includes the ability to choose the distributed arithmetic (DA)-precision bit length, a hardware sharing architecture that reduces the hardware cost, and the proposed time scheduling strategy arranges different dimensional computations in that it can calculate first-dimensional and second-dimensional transformations simultaneously in single 1-D discrete cosine transform (DCT) core to reach a hardware utilization of 100%. The DA-precision bit length is chosen as 9 bits instead of the traditional 12 bits based on test image simulations. In addition, the proposed hardware sharing architecture employs a binary signed-digit DA architecture that enables the arithmetic resources to be shared during the four time slots. For this reason, the proposed 2-D DCT core achieves high accuracy with a small area and a high throughput rate and is verified using a TSMC 0.18-$\mu$m 1P6M CMOS process chip implementation. Measurement results show that the core has a latency of 84 clock cycles with a 52 dB peak-signal-to-noise-ratio and is operated at 167 MHz with 15.8 K gate counts.

We present a new reseeding-mixing method to extend the system period length and to enhance the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG). The reseeding method removes the short periods of the digitized logistic map and the mixing method extends the system period length to 2253by “xoring” with a DX generator. When implemented in the TSMC 0.18- μm 1P6M CMOS process, the new reseeding-mixing PRNG (RM-PRNG) attains the best throughput rate of 6.4 Gb/s compared with other nonlinear PRNGs. In addition, the generated random sequences pass the NIST SP 800-22 statistical tests including ratio test and U-value test.

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

The rapid advance of semiconductor technology exposes multifrequency designs to severe reliability loss due to incomplete at-speed testing, which is induced by ignorance of timing-related defects between clocks. However, the reduced testability caused by core-based design strategy also aggravates the difficulty in applying on-chip at-speed testing. Although previous works were able to successfully increase the quality of the at-speed testing, the diversity of on-chip clock control schemes from different components may complicate the test integration, increasing the test costs. Therefore, to accelerate the time-to-market and the time-to-volume, the development of a plug-and-play at-speed testing based on a well-defined test interface has become increasingly urgent. In this paper, a fast test integration approach for multi-clock-domain at-speed testing based on IEEE Standard 1500 is proposed. The proposed framework has been successfully integrated into an IEEE 1500-wrapped ultrawide-band design and a simple SoC design. Experiment results also confirm the feasibility of the proposed approach.

Rapid advances in semiconductor technology have made timing-related defects increasingly crucial in core-based system-on-chip designs. Currently, modular test strategies based on IEEE standard 1500 are applied to test the functionality of each embedded core in system-on-chip (SoC) designs but fail to verify the corresponding timing specifications. In this paper, to achieve high quality of delay tests, hardware implementation of an embedded delay test framework including the modified test wrappers and the embedded delay test mechanism is presented to build an entirely embedded delay test environment where at-speed clock is applied inside the chip to increase test accuracy. Additionally, the proposed delay test framework is capable of supporting all current solutions of core-based delay test. The experimental results successfully demonstrate the delay testing application using the proposed framework to a crypto processor with satisfying test quality and effectiveness.

For controlling DC-DC converters, variable switching frequency controllers have the advantage of fast transient response since the switching cycles can instantaneously change during the transient condition. However, these control techniques generally suffer significant steady-state switching frequency variation when the input voltage and output voltage are varied. Such drawback complicates the design of input and output filters. Therefore, this paper presents a current mode adaptive on-time control scheme. The proposed controller can dynamically adjust the turn-on time of power switches according to the changes of input voltage and output voltage in steady-state operation and can change switching cycles instantaneously in transient operation. Through the proposed control scheme, the DC-DC converters can accomplish fast transient response with the capability of mitigating the switching frequency variation. Full chip simulation results are provided to verify the proposed method. Comparisons with other control techniques are also presented.

In this paper, a jitter measurement circuit with its calibration scheme for measuring peak-to-peak jitters of clock is proposed and demonstrated. By applying the Vernier oscillators, the mismatching effect and area overhead are both reduced compared with conventional circuits using Vernier delay lines. With high resolution (7.98ps) and high speed (20.08ps/5k samples), the proposed circuit develops a tunable frequency range of input clock and improves the accuracy of the measurement results. The proposed circuit may be applied in multi-clocks' measurement

In this paper, a 32-bit chaos-based pseudo random number generator (PRNG) using timing-based reseeding method with pure digital pseudo noise is proposed for passing the SP 800-22 test. In the iterations of the given chaos equation, when the reseeding timing arrives, the last five least significant bits of the iteration result are masked to produce the pseudo noise, and then the masked result is feedback to the iteration process as a new seed. Using this reseeding method, the proposed PRNG would result in an acceptable quality of randomness without operating in longer bit length digital operation

A time-to-digital Converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated through the proposed approach. In a case-study, by applying the proposed. TDC circuit with 4-bit flash ADC and the accumulated period N=8, the frequency range of the measured signal, resolution and linearity error are 0.7-1.4GHz, 44ps and 1.25%, respectively. Using a 0.25um 1P6M CMOS process, the HSPICE simulation result shows that the maximum measurement error is 1 LSB after calibration.

The voltage difference on bit line pairs is a critical parameter while designing static random access memory (SRAM). In this paper, measurement unit is presented for sampling and amplifying the weak signals of bit line pairs to higher voltage differential level. According to the measured result, the reliability analysis can be easily completed through curve fitting. The proposed circuit is designed and simulated with a IK-bit SRAM by using a 0.18/spl mu/m 1P6M CMOS process. The measured results offer designers a meaningful clue to verify/strengthen their memory design.

In this paper. an embedded built-in-self-test approach for analog-to-digital converters (ADCs) is presented. This architecture can test the parameters of ADC. which includes the differential nonlinearity (DNL) error, integral nonlinearity (INL) error, offset error (V/sub OSE/), gain error (V/sub GE/), and sampling rate. The proposed circuit is designed and simulated with an 8-bit ADC by using a CMOS 0.35 /spl mu/m 1P4M process. The accuracy of DNL test, INL test, VOSE test, and VGE test depend on the testing time. For the case of 256/spl mu/s, the accuracy can achieve 1/10LSB. and longer testing time results in higher accuracy.

As deep sub-micron techniques evolve, embedded memories are dominating the yield, while the testing and measurement issues are more difficult due to access limitations. To solve the testing problem, BIST circuits are developed for testing the functionality of embedded memory, but not for the AC parameters. Based on the dual-slope principle, a new memory access time measurement unit for embedded memories with separate time-to-voltage and voltage-to-time architecture is proposed in this paper to achieve at-speed measurement with 50 ps resolution, where the measurement error is smaller than one LSB, and the linearity error is 1.19%. In conjunction with the March-based BIST circuit, the chip area is 262/spl times/92 /spl mu/m/sup 2/ under a 0.35 /spl mu/m 2P4M CMOS process.

Without a large number of precision reference voltages and with the consideration of matching problems, a builtin-self-test approach is proposed to test the parameters of digital-to-analog converter (DAC), which includes offset error (VOSE); gain error (GFSE), differential nonlinearity (DNL) error, and integral nonlinearity (INL) error. The proposed structure is designed and simulated in an 8-bit DAC by using TSMC 0.35 /spl mu/m 2P4M process. The accuracy of offset error test, gain error test, and DNL test are all beneath 1/11 LSB for 8-bit DAC at 5V supply voltage, and the accuracy of INL test depends on the testing time. The longer testing time, the more accurate is.

A built-in parametric measurement circuit is proposed for time-interval measurement and set-up/hold time measurement. The main idea is based on the dual-slope technique. The minimum resolution is set by resistor array configuration, which is 1/16 clock period in this paper, and easily extendable to desired precision. The imperfection, including the offset voltage and the settling time, is considered to improve the accuracy. Moreover, a simple calibration method is proposed to reduce the measuring error. Experiments on the SRAM access time measurement and the register set-up/hold time measurement show the practicality of the proposed unit.

To explore all faulty behavior on NAND-type flash memory is impractical, and the defects in the SPICE model level are considered. In this paper, two SPICE models of the flash cell are developed and used for circuit-level faulty behavior simulation. The faulty behaviors can be classified to six types and applied for the fault modeling or testing of NAND-type flash memory.

A combined design of four concurrent error detection (CED) schemes-the alternating logic scheme, duplication of the on-set scheme, duplication of the off-set scheme, and the parity checking scheme, is proposed for field programmable logic arrays (FPLAs) which inherently has unutilized elements. One of the four CED schemes can be implemented by the proposed circuit and the unutilized elements with the constraint that the unused elements can be programmed as parts of test logic.>

The yield of ICs has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve the manufacturing and testing processes. This is very costly and quite difficult to implement. The practical approach is to use a fault-tolerant design. In this paper, a design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired with-out reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and has led to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.

When a multiple-output function is realized by a PLA (programmable logic array), there is often the option of realizing either true or complementary logic for each output. The tradeoffs in implementing PLAs with and without output phase assignment are explored, and an efficient output phase assignment for PLA minimization is presented. The results of this study show that the proposed algorithm reduces the number of product terms by as much as 50% when the output phase assignment is considered.>