What do computing industry practitioners—varying in age, experience, and culture—think of undergraduate computer science (CS) education? What do they value the most based on their own experiences and what do they see in the graduates they hire or work with? These were some of the questions addressed by a collaborative effort of eight universities across the US. This effort ultimately led to a collaboration with the Computing Research Association (CRA), which launched a national-scale Practitioner-to-Professor (P2P) Survey in 2024 that provides useful information for CS educators. Unlike broad all-major surveys, P2P focuses on CS with the detail needed for actionable feedback. This special session summarizes the results from the 2024 P2P administration, including several surprising outcomes, and engages participants to reflect on how the P2P results could help their programs improve their graduate readiness for long-term career success. Attendees will also learn how they can propose questions for future P2P surveys.

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

This experience report describes an attempt to improve student attitudes towards exams by encouraging students to craft exam questions that earn game points and by allowing students to defer some questions to a second attempt at the exam a week later, increasing study time while reducing common timed-test anxiety. The approach, inspired by research in gamification and student-generated questions, focuses on: getting students to study broadly across the material; encouraging students to craft good questions; encouraging an honest first attempt; preventing memorization for the second attempt; incorporating teamwork. Data collected from implementations in two different courses indicate that several finer points of the game design are important and that student-generated questions can be just as effective as instructor-generated questions. Survey data shows that students are very positive about having a second chance at learning.

Recent work [Erikson et al 2017 and Zavala et al 2018] has shown that mental program-execution exercises, in the form of Parson's puzzles or program-tracing, are effective in improving student performance in intro CS courses. This form of practice is promising because its low cost of creation and short duration (for the student) can promote the significant practice needed for learning. The goal of this paper is to enable wider use of such exercises through large-scale automated generation of short, multiple-choice mental execution questions. The challenge in automation is to algorithmically generate effective distractors (plausible, but incorrect choices), and to generate questions of varying levels of difficulty and whose difficulty level can be set by the instructor. In this paper, we propose a language-generalizable approach for automatically generating a practically unlimited number of such exercises, each constructed to a designated level of difficulty and incorporating the core programming-in-the-small themes: assignment, conditionals, loops, and arrays. The stochastic tree-based generation algorithm and a subsequent simulation of execution also enable generating effective distractors since all possible execution paths are readily available in the tree at the time of generation, and the distractors, therefore, correspond to reasonable (but ultimately incorrect) paths of execution. Furthermore, the approach is easily transferable to other languages with little effort. The generated questions are delivered through a mobile app that can be customized by the instructor to vary the questions generated and to introduce interleaving to take advantage of the spacing effect. Preliminary student feedback on the experience has been positive.

This study presents and evaluates a scalable approach for improving learning outcomes by having students "teach" peers in the same course via video. The approach was tested in a standard upper-level undergraduate computer algorithms course with material commonly considered challenging to teach: combinatorial optimization and NP-complete problems. An important design goal was to incentivize students to learn deeply in crafting their instructional videos while minimizing the added burden on instructors to review their products, allowing for scalability. A learning assessment administered to two successive cohorts (N=89) showed statistically significant improvement (P<0.0001) in learning for students who make the videos compared to those who merely study the materials or view the videos. Students not only enjoyed applying their creativity in making videos but, in the process, also strengthened their conceptual learning. While much of the existing research on student-created videos has shown its effectiveness in motivating students, few studies exist that directly isolate learning gains in those who craft instructional videos.

The protection of information in enterprise and cloud platforms is growing more important and complex with increasing numbers of users who need to access resources with distinct permissions. Role-based access control (RBAC) eases administrative complexity for large-scale access control, while a client-server model can ease performance bottlenecks by distributing access enforcement across multiple servers that consult the centralized access decision policy server as needed. In this paper, we propose a new approach to access enforcement using an existing associative array hardware data structure (HWDS) to cache authorizations in a distributed system using RBAC. This HWDS approach uses hardware that has previous been demonstrated as useful for several application domains including access control, network packet routing, and generic comparison-based integer search algorithms. We reproduce experiments from prior work on distributed access enforcement for RBAC systems, and we design and conduct new experiments to evaluate HWDS-based access enforcement. Experimental data show the HWDS cuts session initiation time by about a third compared to existing solutions, while achieving similar performance to authorize access requests. These results suggest that distributed systems using RBAC could use HWDS-based access enforcement to increase session throughput or to decrease the number of access enforcement servers without losing performance.

Modern programs comprise multiple threads of execution inside a single principal -- the process -- with a single protection domain, usually a page table. We propose a hardware enforced, fine-grained memory protection mechanism to divide the process into smaller principals and multiple protection domains. Our approach supports modern software engineering better than traditional processes by enabling developers to align software components with protection mechanisms. We implemented our architecture using a cycle-accurate simulator of a complex out-of-order pipeline and evaluate our solution using open-source benchmarks and synthetic micro benchmarks designed specifically to stress our system.

Hardware support can reduce the time spent operating on data structures by exploiting circuit-level parallelism. Such hardware data structures (HWDSs) can reduce the latency and jitter of data structure operations, which can benefit real-time systems by reducing worst-case execution times (WCETs). For example, a hardware priority queue (HWPQ) can enqueue and dequeue prioritized items in constant time with low variance; the best software implementations are in logarithmic-time asymptotic complexity for at least one of the enqueue or dequeue operations. The main problems with HWDSs are the limited size of hardware and the complexity of sharing it. In this paper we show that software support can help circumvent the size and sharing limitations of hardware so that applications can benefit from a HWDS. We evaluate our work by showing how the choice of software or hardware affects schedulability of task sets that use multiple priority queues of varying sizes. We model task behavior on two applications that are important in real-time and embedded domains: the grey-weighted distance transform for topology mapping and Dijkstra's algorithm for GPS navigation. Our results indicate that HWDSs can reduce the WCET of applications even when a HWDS is shared by multiple data structures or when data structure sizes exceed HWDS size constraints.

Embedded systems of an inherently distributed and highly replicated nature are vulnerable to a class of attacks that require local access and physical tampering. Processors using Encrypted Execution and Data (EED) technology, where instructions and data are stored in encrypted form in memory and locally decrypted, form an attractive solution for securing embedded systems, as these platforms have been shown to protect software and limit information leakage. However, numerous realistic attacks are still possible on EED platforms given the assumption of an adversary with physical access. In this paper, we present an integrated compiler and architectural approach to address a class of memory spoofing attacks, in which a sophisticated attacker is able to control off-chip buses and modify data blocks as they are loaded into the processor. Our approach, which utilizes cache boundaries to greatly simplify the integrity checking process, prevents an attacker from tampering, injecting, or replaying code and data. We make use of an on-chip reconfigurable logic component to implement our security mechanisms. This use of reconfigurable logic greatly simplifies the required hardware modifications - no changes are necessary to the CPU, cache, or off-chip memory. Our simulations on a number of benchmarks show that a high level of security can be achieved with a low performance overhead. The average overhead incurred is dependent on the cache size and type of integrity checking scheme used, but is less than 16% even for the most computationally intensive scheme. We present a hardware/software prototype mapped to a Field Programmable Gate Array (FPGA) platform in order to evaluate the space required and demonstrate the feasibility of our approach.

Cluster-based servers delivering timely responsive service can shorten response latency and maximize system throughput through multi-threading. However, under high workload, large volume of threads may overload the kernel, leading to an inoperational system "hold-out" status. Majority of overload control work have been done at application level, but lack the collaboration between application and kernel to proactively respond to overloading. In this paper we propose two application-kernel cooperative mechanisms, of which the Flush-Out function recovers system from overloading by filtering out certain amount of events from kernel, and the Early-Drop mechanism protects system from overloading by proactively responding to load status. Experiments on a cluster server indicate the proposed mechanisms improve serverpsilas responsiveness under high load condition by substantially cutting the response time by 7~22% and event drop rate to 10~21%. The application-kernel mechanisms demonstrate its effectiveness in keeping mission-critical servers in operational state and delivering improved performance under high .workload.

Software security has become a prominent area of research in recent years, with research efforts spanning a wide range of topics. Among these are techniques such as those in this paper that are in the general area of languages, compilers and architecture aimed at increasing the security of computing systems. This paper describes a compiler technique that performs risk-analysis on source code and generates an encrypted executable that both provides security but yet reduces overhead by selectively encrypting low-risk portions with less overhead. Regions of the code that are more vulnerable receive a higher degree of encryption. Experimental results for this technique, which we call Region-Based Security, using a collection of benchmarks show that execution overhead is reduced considerably by using this approach.

Hypoxia induces the expression of genes that alter metabolism through the hypoxia-inducible factor (HIF). A theoretical model based on differential equations of the hypoxia response network has been previously proposed in which a sharp response to changes in oxygen concentration was observed but not quantitatively explained. That model consisted of reactions involving 23 molecular species among which the concentrations of HIF and oxygen were linked through a complex set of reactions. In this paper, we analyze this previous model using a combination of mathematical tools to draw out the key components of the network and explain quantitatively how they contribute to the sharp oxygen response. We find that the switch-like behavior is due to pathway-switching wherein HIF degrades rapidly under normoxia in one pathway, while the other pathway accumulates HIF to trigger downstream genes under hypoxia. The analytic technique is potentially useful in studying larger biomedical networks.

One of the key problems facing the computer industry today is ensuring the integrity of end-user applications and data. Researchers in the relatively new field of software protection investigate the development and evaluation of controls that prevent the unauthorized modification or use of system software. While many previously developed protection schemes have provided a strong level of security, their overall effectiveness has been hindered by a lack of transparency to the user in terms of performance overhead. Other approaches take to the opposite extreme and sacrifice security for the sake of this transparency. In this work we present an architecture for software protection that provides for a high level of both security and user transparency by utilizing field programmable gate array (FPGA) technology as the main protection mechanism. We demonstrate that by relying on FPGA technology, this approach can accelerate the execution of programs in a cryptographic environment, while maintaining the flexibility through reprogramming to carry out any compiler-driven protections that may be application-specific.

The new-found ubiquity of embedded processors in consumer and industrial applications brings with it an intensified focus on security, as a strong level of trust in the system software is crucial to their widespread deployment. The growing area of software protection attempts to address the key steps used by hackers in attacking a software system. In this paper, we introduce a unique approach to embedded software protection that utilizes a hardware/software codesign methodology. Results demonstrate that this framework can be the successful basis for the development of embedded applications that meet a wide range of security and performance requirements.

A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software protection attempts to address the key steps used by hackers in attacking a software system. In this paper we present an efficient and tunable approach to some problems in embedded software protection that utilizes a hardware/software codesign methodology. By coupling our protective compiler techniques with reconfigurable hardware support, we allow for a greater flexibility of placement on the security-performance spectrum than previously proposed mainly-hardware or software approaches. Results show that for most of our benchmarks, the average performance penalty of our approach is less than 20%, and that this number can be greatly improved upon with the proper utilization of compiler and architectural optimizations.

Growing concerns regarding application security and software piracy have motivated research in systems that ensure an increased level of tamper resistance while limiting the effectiveness of malicious attacks. These approaches have ranged from simple code restructuring techniques containing run-time checks to complex cryptographic systems. In this work we propose a reconfigurable software protection architecture that places an FPGA between the highest level of on-chip cache and main memory. Instructions requested by the processor are passed through the FPGA component after being fetched from memory. The task of the FPGA is to validate and also possibly transform the instructions in some fashion before sending them back to the processor. As the FPGA configuration can be customized to individual applications, the resultant system can be flexible in meeting both security and performance requirements. Our initial results show that a strong level of security can be obtained with only a limited performance overhead.

In a wireless network some nodes incur a disproportionate share of the packet forwarding burden than the others: nodes lying toward the center tend to lie on more paths and therefore expend more energy in forwarding packets than other nodes, resulting in a shorter lifetime. While routes can be selected to alleviate this problem, we explore an entirely different and complementary approach by exploiting a wireless node's capability to adjust its transmission power. Each connection is partitioned into two segments, each of which uses the regular network or direct transmission between the source and the destination. The relative durations of each segment are optimized to balance energy consumption across the network. This paper formulates an energy balance optimization problem in terms of the segmentation time, and an algorithm is presented that reduces variance in energy consumption at the cost of a modest increase in average energy consumption. The paper also presents a distributed algorithm for this optimization problem.

Wireless sensor networks have recently attracted lots of research effort due to the wide range of applications. These networks must operate for months or years. However, the sensors are powered by battery, which may not be able to be recharged after they are deployed. Thus, energy-aware network management is extremely important. In this paper, we study the following problem: Given a set of sensors in the plane, assign transmit power to each sensor such that the induced topology containing only bidirectional links is strongly connected. This problem is significant in both theory and application. We prove its NP-completeness and propose two heuristics: power assignment based on minimum spanning tree (denoted by MST) and incremental power. We also show that the MST heuristic has a performance ratio of 2. Simulation study indicates that the performance of these two heuristics does not differ very much, but; on average, the incremental power heuristic is always better than MST.

An important sub-topic in survivable topology design is the augmentation of existing topologies to enable surviving node or link failures. The general topology augmentation problem addresses the general question: what additional resources are required to build upon an existing network to enhance its survivability? A typical such problem involves finding the fewest links to add to a topology to make the topology 2-edge-connected. This paper considers a variation of that problem: given a topology, a set of potential links each with a cost, and a limited budget, find links that can be added to enhance the topology's biconnectivity. This variation is useful for the case where expansion of a topology is constrained by a limited budget. The problem is shown to be NP-complete. Three simple heuristics are presented and evaluated through experimentation. The main result is that simple greedy heuristics that reduce cost are not effective because the problem structure combines both costs and paths in unusual ways. Instead, a suite of heuristics appears to perform effectively.

This paper studies-the off-line wavelength assignment problem in star and ring networks that deploy multiple fibers between nodes and use wavelength division multiplexing (WDM) for transmission. The results in this paper show that the ability to switch between fibers increases wavelength utilization. In particular, sharper per-fiber bounds on the number of required wavelengths are derived for the multifiber version of the assignment problem in star and ring networks. Additionally, the complexity of the problem is studied and several constrained versions of the problem are also considered for star and ring networks. A summary of contributions is provided.

This paper studies the off-line wavelength assignment problem in star and ring networks that deploy multiple fibers between nodes and use wavelength division multiplexing (WDM) for transmission. The results in this paper show that the ability to switch between fibers increases wavelength utilization. In particular, sharper per-fiber bounds on the number of required wavelengths are derived for the multifiber version of the assignment problem in star and ring networks. Additionally, the complexity of the problem is studied and several constrained versions of the problem are also considered for star and ring networks. A summary of contributions is provided in the first section.

This paper presents an experimental study of dynamic load balancing methods for a parallelized solution to a well-known problem in computational molecular biology: computing the accessible surface areas (ASA) of proteins. The main contribution is a better understanding of how certain techniques for load estimation and redistribution must be combined carefully for effectiveness and how these combinations need to change during the course of a computation. In particular, the Shrake-Rupley ASA algorithm is implemented and three aspects of dynamic load balancing are studied: how to estimate load imbalance (the estimation problem); when to invoke load redistribution (the invocation problem); and how to load balance (the mapping problem). The results in this paper show that a dynamically-selected mix of algorithms in each category that adapts to changing structure within the protein works better than a static periodic application of a static mix of algorithms.

This paper considers the problem of allocating files in a document tree among multiple processors in a parallel webserver. It is assumed that access patterns are characterized by branching probabilities for an access that starts at a node and progresses down the tree. A combinatorial optimization problem is formulated that includes load balancing and communication costs. The general problem is shown to be NP-complete, and a pseudo-polynomial time algorithm is outlined. In addition, two fast heuristic algorithms are presented and evaluated using simulation.

We consider the problem of statically assigning many tasks to a (smaller) system of homogeneous processors, where a task's structure is modeled as a branching process, all tasks are assumed to have identical behavior, and the tasks may synchronize frequently. We show how the theory of majorization can be used to obtain a partial order among possible task assignments. We show that if the vector of numbers of tasks assigned to each processor under one mapping is majorized by that of another mapping, then the former mapping is better than the latter with respect to a large number of objective functions. In particular, we show how the metrics of finishing time, the space-time product, and reliability are all captured. We also apply majorization to the problem of partitioning a pool of processors for distribution among parallelizable tasks. Limitations of the approach, which include the static nature of the assignment, are also discussed.

We study the problem of placing erasure nodes among passive stations in a slotted dual bus network. Erasure nodes are known to improve throughput by allowing slot reuse. It is also known that choices made in locating erasure nodes significantly impact network congestion and overall throughput-especially when traffic patterns exhibit a high degree of locality. We present algorithms to determine optimal placements of erasure nodes that improve upon prior work on this problem: we present simpler and faster polynomial-time algorithms and also consider various useful cost measures. These algorithms can be used to solve related placement problems in which limits on congestion and existing placements are given as input, and the goal is to find the minimum number of erasure nodes required to meet the congestion bound.

Traditionally, allocation of data in distributed database management systems has been determined by off-line anidysis and optimization.This technique works well for static database access patterns, but is often inadequate for frequently changing workloads.This paper addresses the problem of dynamically reallocating data in a partionable distributed database with changing access patterns.Rather than complicated and expensive optimization algorithms, a simple heuristic is presented and shown, via an implementation study, to improve system throughput by 3070 in a local area net work based system.For a wide area network the performance gain is expected to be even larger.It is also shown that individual site load must be taken into consideration when reallocating data.A a simple policy that incorporates load in the reallocation decision is provided.1

This paper considers the problem of estimating, via simulation, extremely low packet loss rates in a voice-data multiplexer. The multiplexer gives priority to voice packets, unless the data queue length exceeds a threshold. To efficiently simulate such low loss rates requires the proper use of importance sampling. In this paper we describe an importance sampling technique that is guaranteed to provide an exponential decrease in variance over standard simulation. This importance sampling technique has two phases, with a different importance sampling strategy in each phase. Experimental results are presented that demonstrate the effectiveness of this approach.

With the addition of new network services, it is anticipated that the processing involved in setting up a call in a circuit-switched network or a session in a packet-switched network will vary greatly for different types of services. In this paper, we address the problem of reducing the call setup time in a circuit-switched network, or equivalently the session setup time in a packet-switched network, through the balancing of load across call processors. With a view to designing algorithms to execute on-line in a system, we formulate a stochastic optimization problem and study the use of stochastic approximation techniques. Given the distributed nature of the problem, we extend previous results obtained for a single node to the case where several nodes operate simultaneously and in an asynchronous manner. Our results include a theoretical study of convergence as well as several simulation results that compare two stochastic approximation techniques.>

The availability of large-scale multitasked parallel architectures introduces the following processor assignment problem. We are given a long sequence of data sets, each of which is to undergo processing by a collection of tasks whose intertask data dependencies form a series-parallel partial order. Each individual task is potentially parallelizable, with a known experimentally determined execution signature. Recognizing that data sets can be pipelined through the task structure, the problem is to find a "good" assignment of processors to tasks. Two objectives interest us: minimal response time per data set, given a throughput requirement, and maximal throughput, given a response time requirement. Our approach is to decompose a series-parallel task system into its essential "serial" and "parallel" components; our problem admits the independent solution and recomposition of each such component. We provide algorithms for the series analysis, and use an algorithm due to Krishnamurti and Ma for the parallel analysis. For a p processor system and a series-parallel precedence graph with n constituent tasks, we give a O(np/sup 2/) algorithm that finds the optimal assignment (over a broad class of assignments) for the response time optimization problem; we find the assignment optimizing the constrained throughput in O(np/sup 2/ log p) time. These techniques are applied to a task system in computer vision.>

The authors consider the static load balancing problem of assigning several large tasks to a (smaller) system of homogeneous processors, where a task's structure is modeled as a branching process, and all tasks are assumed to have stochastically identical behavior. They show how the theory of majorization can be used to obtain a partial order among possible task assignment. The power of this approach may be summarized as follows: a simple comparison between assignments creates an ordering between them that holds for a variety of objective functions as well as for several statistics such as the mean and variance. This partial ordering is particularly useful when heterogeneous constraints are placed on the numbers of tasks that one may assign to the processors. The results show that if the vector of numbers of tasks assigned to each processor under one mapping is majorized by that of another mapping, then the former mapping is better than the latter with respect to a large number of objective functions. In particular, it is shown how measurements of finishing time, resource utilization, and reliability are all captured by the theory.>

The authors consider a queuing system with a finite buffer and multiple heterogeneous arrival streams. They focus on Markov modulated arrival processes with different burstings and investigate the loss of individual arrival streams when the parameters of the heterogeneous arrival streams are varied. The analysis includes both continuous-time and discrete-time treatments of multiplexed heterogeneous Markov modulated arrivals. Loss probabilities are derived for a priority packet discarding scheme. A new characterization of an arrival stream is introduced, referred to as a self-loss, and it is used to qualitatively predict the effects of multiplexing bursty streams with nonbursty streams. The effectiveness of priority packet discarding is also investigated through numerical examples.>

The authors address the problem of reducing the call setup time in a circuit-switched network, or, equivalently, the session setup time in a packet-switched network, through the balancing of load across call processors. A stochastic optimization problem is formulated, and the use of stochastic approximation techniques is studied. Given the distributed nature of the problem, previous results obtained for a single node are extended to the case where several nodes operate simultaneously and in an asynchronous manner. A theoretical study of convergence as well as several simulation results that compare two stochastic approximation techniques are presented.>

Decentralized algorithms are examined for optimally distributing a divisible resource in a distributed computer system. To study this problem in a specific context, the problem of optimal file allocation is considered. In this case, the optimization criteria include both the communication cost and average processing delay associated with a file access. The algorithms examined have their origins in the field of mathematical economics. They are shown to have several attractive properties, including their simplicity and distributed nature, the computation of feasible and increasingly better resource allocations as the result of each iteration, and, in the case of file allocation, rapid convergence. Conditions are formally derived under which the algorithms are guaranteed to coverage, and their convergence behavior is additionally examined through simulation.>

A novel class of action probability update algorithms for learning automata that use the relative reward strengths of responses from the environment is examined. Specifically, update algorithms for S-model automata in which 'recent' environmental responses for each of the actions retained are used. A convergence result is proven and the behavior of these automat is studied by simulation. A major result is that the performance of these algorithms is superior, in several respects, to that of the well-known SL/sub R-1/ update algorithm. Additional results are presented on the variability of performance, the cost of learning and, in the case of static environments, modifications that result in improved convergence.>