Demo Data from EDBT 2026 / reviewers in the wild / expert
Philip L. Vitale
dblp:24/4065
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 33% Processor architecture and microarchitecture · 33% Memory systems · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › cache coherence
cache-coherent shared memory |
0.0 | 1 | 1990 | Performance Evaluation of a Commercial Cache-Coherent Shared Memory Multiprocessor · SIGMETRICS 1990 |
Performance modeling and evaluation › queueing models
mean value analysis |
0.0 | 1 | 1990 | Performance Evaluation of a Commercial Cache-Coherent Shared Memory Multiprocessor · SIGMETRICS 1990 |
Processor architecture and microarchitecture › multiprocessor architecture
symmetric multiprocessor |
0.0 | 1 | 1990 | Performance Evaluation of a Commercial Cache-Coherent Shared Memory Multiprocessor · SIGMETRICS 1990 |
Methods — techniques the papers use, named apart from their topics
approximate mean value analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | Performance Evaluation of a Commercial Cache-Coherent Shared Memory MultiprocessorabstractThis paper describes an approximate Mean Value Analysis (MVA) model developed to project the performance of a small-scale shared-memory commercial symmetric multiprocessor system. The system, based on Hewlett Packard Precision Architecture processors, supports multiple active user processes and multiple execution threads within the operating system. Rajeev Jog, Philip L. Vitale, James R. Callister |
SIGMETRICS | 2 |