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EDBT 2026 Demo / reviewers in the wild / expert

J. M. Herron

dblp:24/4183 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1982
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Parallel and multicore computing · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › image processing accelerator
image analysis accelerator		 0.011982
A General-Purpose High-Speed Logical Transform Image Processor · IEEE Trans. Computers 1982
Parallel and multicore computing › parallel architecture
parallel processor		 0.011982
A General-Purpose High-Speed Logical Transform Image Processor · IEEE Trans. Computers 1982

Methods — techniques the papers use, named apart from their topics

table lookup · 0.0logical transform · 0.0
YearPublicationVenuePosition
1982 A General-Purpose High-Speed Logical Transform Image Processor
abstract
A new logical transform processor has been designed and its performance presented in this correspondence. The design incorporates the speed advantage of a locally parallel processor and yet has the capability of processing images of widely ranging dimension. Sixteen pixels are processed simultaneously using table lookup. Image size and neighborhood size are under program control of the host computer, a Perkin-Elmer 3220. This logical transform processor is capable of executing picture point operations in 50 ns.
J. M. Herron, J. Farley, Kendall Preston Jr., H. Sellner
 IEEE Trans. Computers1