High-bandwidth memory (HBM) has enabled substantial advancements in bandwidth-intensive applications, including large-scale artificial intelligence models. HBM is typically integrated with other systems-on-chip (SoCs) through a silicon interposer, and the primary bottleneck in aggressively scaling the bandwidth in next-generation HBM systems stems from significant crosstalk caused by closely spaced, high-density parallel interconnects in the interposer. While crosstalk avoidance code (CAC) has emerged as a promising solution, prior CAC schemes suffer from low bit efficiency and considerable hardware overhead. This article proposes an efficient CAC scheme, WITCH, which employs a novel weighted coding strategy. Unlike prior approaches that consider all channels identically, WITCH assigns different weights to channels based on their relative positions in the array, enabling more bit-efficient crosstalk suppression. We also present WITCH with additional shielding (WITCH-AS), an extension of WITCH that incorporates additional shielding to further reduce crosstalk levels. Our coding schemes achieve high bit efficiency, up to 17.3% higher than state-of-the-art techniques while providing an identical level of crosstalk reduction. Simulation results using an industry-proven channel model demonstrate that WITCH and WITCH-AS improve eye height by 10.1%–49.4% and 17.1%–51.1%, respectively. Furthermore, we propose an area- and energy-efficient hardware implementation that can be integrated into real-world HBM systems. The design reduces area and critical path delay by 31.0% and 28.2%, respectively, compared with conventional designs. Finally, we propose a compatible simultaneous switching output (SSO) noise mitigation technique that can be seamlessly integrated into WITCH to further enhance signal integrity under high-speed, high-density operating conditions.

High bandwidth memory (HBM) has enabled a breakthrough in bandwidth-bound applications, including large-scale artificial intelligence models. HBM is typically connected to other SoCs through a silicon interposer. However, the increasing density of the parallel interconnect wires incurs significant amount of crosstalk, hindering bandwidth improvement in the next-generation HBMs. While Crosstalk Avoidance Code (CAC) has emerged as a solution to mitigate crosstalk, prior CAC schemes suffer from low bit efficiency and significant hardware overhead. This paper proposes an efficient CAC scheme, WITCH. It employs a new coding system, weighted coding, which gives a different emphasis to each channel according to its relative position in the channel array. This enables crosstalk reduction with higher bit efficiency than prior CACs treating all channels in the array equally. The extended version of WITCH, WITCH-AS, is also proposed with additional shielding for further crosstalk reduction. Our coding system shows high bit efficiency of 91.2--91.7% and 84.3--84.6% for WITCH and WITCH-AS, which is up to 20.8% higher than the state-of-the-art schemes while preserving the same crosstalk level reduction. We have shown through simulations using an industry-proven channel model that WITCH and WITCH-AS improve the eye heights by 10.1--49.4% and 17.1--51.1% respectively. In addition, this paper presents an efficient hardware implementation of our coding schemes which shows 28.2% lower critical path delay and 31.0% smaller area than conventional implementation, proving itself a practical solution for HBMs.

Silicon photonics integrates both photonic and electronic components on the same silicon chip and promises ultra-dense, high-bandwidth interconnects via wavelength division multiplexing (WDM). However, when verifying such silicon photonic systems, the existing IC simulators face challenges due to the WDM signals containing multiple frequency tones at ~200-THz with ~50-GHz spacing. This paper presents a systematic approach to modeling the silicon photonic elements and devices as equivalent multi-port transmission lines using XMODEL primitives and simulating the WDM link models in an efficient, event-driven fashion in SystemVerilog. The 5Gb/s, 3-channel WDM link models with micro-ring, Mach-Zehnder, and electro-absorption modulators demonstrate the simulation speeds of 4.2, 8.3, and 8.3 symbols/second, respectively.

In real-world scenarios, image recognition tasks, such as semantic segmentation and object detection, often pose greater challenges due to the lack of information available within low-resolution (LR) content. Image super-resolution (SR) is one of the promising solutions for addressing the challenges. However, due to the ill-posed property of SR, it is challenging for typical SR methods to restore task-relevant high-frequency contents, which may dilute the advantage of utilizing the SR method. Therefore, in this paper, we propose Super-Resolution for Image Recognition (SR4IR) that effectively guides the generation of SR images beneficial to achieving satisfactory image recognition performance when processing LR images. The critical component of our SR4IR is the task-driven perceptual (TDP) loss that enables the SR network to acquire task-specific knowledge from a network tailored for a specific task. Moreover, we propose a cross-quality patch mix and an alternate training framework that significantly enhances the efficacy of the TDP loss by addressing potential problems when employing the TDP loss. Through extensive experiments, we demonstrate that our SR4IR achieves outstanding task performance by generating SR images useful for a specific image recognition task, including semantic segmentation, object detection, and image classification. The implementation code is available at https://github.com/JaehaKim97ISR4IR.

This paper analyzes the phase tracking capability of a fractionally-spaced equalizer (FSE) to propose a dedicated equivalent model as a clock and data recovery (CDR) loop. In contrast to reported FSE studies, our study focuses on quantitative determinations for equivalent CDR loop parameters pertinent to practical CDR designs using FSE. By analyzing second-order statistics and eigenmodes for finite-impulse response (FIR) transversal filter-based FSE as a function of the entire sampling phases, we can estimate the bandwidth tied to the critical eigenmode and additive mean-squared error (MSE). This analysis can guarantee the worst-case behavior of the FSE as a CDR. The behavioral simulation results show the effectiveness of the proposed CDR model by demonstrating the error transfer function, jitter tolerance (JTOL), and bit-error-rate (BER). Based on the analysis, an enhanced decision scheme for the FSE-alternating technique is proposed. The behavioral simulation result shows a 38.5% reduction in the standard deviation of error compared to our previous work for an infinite-range plesiochronous system.

Hands, one of the most dynamic parts of our body, suffer from blur due to their active movements. However, previous 3D hand mesh recovery methods have mainly focused on sharp hand images rather than considering blur due to the absence of datasets providing blurry hand images. We first present a novel dataset BlurHand, which contains blurry hand images with 3D groundtruths. The BlurHand is constructed by synthesizing motion blur from sequential sharp hand images, imitating realistic and natural motion blurs. In addition to the new dataset, we propose BlurHandNet, a baseline network for accurate 3D hand mesh recovery from a blurry hand image. Our BlurHandNet unfolds a blurry input image to a 3D hand mesh sequence to utilize temporal information in the blurry input image, while previous works output a static single hand mesh. We demonstrate the usefulness of BlurHand for the 3D hand mesh recovery from blurry images in our experiments. The proposed BlurHandNet produces much more robust results on blurry images while generalizing well to in-the-wild images. The training codes and BlurHand dataset are available at https://github.com/laehaKim97IBlurHand_RELEASE.

Most image super-resolution (SR) methods are developed on synthetic low-resolution (LR) and high-resolution (HR) image pairs that are constructed by a predetermined operation, e.g., bicubic downsampling. As existing methods typically learn an inverse mapping of the specific function, they produce blurry results when applied to real-world images whose exact formulation is different and unknown. Therefore, several methods attempt to synthesize much more diverse LR samples or learn a realistic downsampling model. However, due to restrictive assumptions on the downsampling process, they are still biased and less generalizable. This study proposes a novel method to simulate an unknown downsampling process without imposing restrictive prior knowledge. We propose a generalizable low-frequency loss (LFL) in the adversarial training framework to imitate the distribution of target LR images without using any paired examples. Furthermore, we design an adaptive data loss (ADL) for the downsampler, which can be adaptively learned and updated from the data during the training loops. Extensive experiments validate that our downsampling model can facilitate existing SR methods to perform more accurate reconstructions on various synthetic and real-world examples than the conventional approaches.

This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust 2 × residue amplification by subtracting two pulse widths. First, the input voltage is converted into two timing pulses containing the information of the time difference between their rising edges. Each MDAC stage performs 1.5-bit quantization and generates two turn-on pulses with pulse widths bearing the opposite signs of the residue, + Tresand -Tres. The following pair of integrate-and-fire circuits, each containing a current source charging a capacitor to a threshold voltage, computes the difference between the two pulse widths, Tres-(-Tres)=2Tres, and generates new timing pulses bearing the 2× amplified residue for the next stage. The circuit non-idealities in the MDACs contribute to the offset errors but not to the gain errors in their transfer curves, making the calibration simple. Moreover, the ADC does not require amplifiers, making it suitable for low-voltage digital processes. The prototype 10-bit pipelined ADC fabricated in 28-nm CMOS dissipates 1.55-mW at 125-MS/s and occupies 0.025 mm2. With signal-to-noise and distortion ratio of 44.3 dB and spurious-free dynamic range of 53 dB for a 1-MHz sinusoidal input, the ADC has a figure of merit of 96.8-fJ/conversion step.

The sensing system in NAND flash memories is a complex mixed-signal circuit consisting of a large-scale cell array, wordline decoders, page buffers, analog/digital bit-counters, and digital sequence controllers. This paper proposes a model and simulation framework that can assess the effectiveness of various incremental/adaptive algorithms used by digital controllers for the read, program, and erase operations, while simulating the progression of individual cell threshold voltages (Vth) and modeling the detailed analog characteristics of the page buffers. The proposed model is written entirely in SystemVerilog, and its analog parts are described using the XMODEL primitives, which enable efficient and event-driven simulation of analog circuits. The proposed model can simulate a 40μs-long incremental step pulse programming (ISPP) sequence with the maximum loop iteration count of 4 on a 12K-bit block of single-level cells (SLC) in less than 2 minutes, and can assess the trade-offs between the programming speed and reliability as a function of the pulse step size and the impacts of the page buffer's sensing time on the final cell Vth distribution.

Upon the observation of a circuit failure, problematic circuit blocks and parameters need to be localized before they can be fixed or bypassed -- this has traditionally been highly manual and problem-specific. In this paper, we present a bug localization methodology that automatically identifies and ranks potential root-causes probabilistically. We model linear and nonlinear sub-circuits using the corresponding probabilistic graphical models, and formulate the bug localization problem as a statistical inference problem given partially observed data. We infer the posterior distribution of underlying circuit parameters, which provides a statistical measure of whether the bug lies in each sub-circuit. We have verified this methodology on a high-speed I/O link circuit, and have demonstrated its effectiveness of root-causing circuit bugs.

An on-chip measurement technique for characterizing the jitter tolerance (JTOL) of high-speed receivers is presented. A JTOL test finds the largest sinusoidal jitter (SJ) in the input data stream that the receiver can tolerate and its test typically requires an expensive equipment to impose SJ on the data and long time to repeatedly measure the bit-error rates. The proposed technique emulates the SJ in the off-chip input data stream with a SJ in the on-chip recovered clock of the clock-and-data recovery loop (CDR), allowing an ordinary transmitter to be used as the input source. Furthermore, the testing time is reduced by measuring the CDR bandwidth and timing margin separately, using a linear ramp and step jitters instead of SJ. The in-situ JTOL measurement circuit is demonstrated for a feed-forward phase-interpolating dual-loop CDR, in which the SJ is emulated by applying a digital-valued phase offset to the recovered clock. Implemented in a 65nm CMOS, the circuit occupies only 480μm2, 1.8% of the total CDR area. Yet, it can accurately measure the JTOL characteristics of the CDR with 20× shorter testing time.

This paper explores the use of discrete optimization techniques for variability-aware analog circuit synthesis, with an observation that the continuous design space can be effectively covered by a finite number of discrete points when parameter variation is present. Three algorithms are described that can leverage a discretized design space yet mitigate its dimensionality scaling problem: an isotropic discretization scheme, which can fill the neighborhood of any given point with only quadratically-increasing number of nearest neighbors placed at equal distances as the space dimension increases, a stochastic hill-climbing algorithm, which evaluates only a partial set of nearest neighbors yet finds the local optimum at the reduced cost, and an incremental Monte Carlo sampling algorithm, which draws the minimal number of Monte Carlo samples just enough to determine the superior design point during the local search process. These algorithms help in finding the optimal design of analog circuits efficiently. For instance, for a digitally-controlled oscillator example, its discretized design space consists of 5 565 907 points but the optimal point was found by evaluating only 40 design points and running only 21 Monte Carlo simulations per point in average (824 in total).

This paper presents an efficient method for extracting a yield-aware Pareto front between two competing metrics of an analog circuit block, with the purpose of performing hierarchical, system-level optimization using the component-level Pareto fronts as meta-models. The proposed method consists of three steps: finding a set of Pareto-optimal design points by tracing them on a discrete grid, estimating the yield distribution of each optimal design point using a control-variate technique, and constructing a yield-aware Pareto front by interpolation. The proposed algorithm is demonstrated on a problem of finding the optimal power allocation among the components composing a clock recovery path to minimize the final clock jitter. The algorithm can estimate the Pareto front of each circuit block within a 2% error, expressing the minimum achievable jitter with 99% yield for different power budgets, while requiring only 600 ~ 1100 Monte-Carlo simulation samples in total.

A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a high-rate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation.

Memory bandwidth has been one of the most critical system performance bottlenecks. As a result, the HMC (Hybrid Memory Cube) has recently been proposed to improve DRAM bandwidth as well as energy efficiency. In this paper, we explore different system interconnect designs with HMCs. We show that processor-centric network architectures cannot fully utilize processor bandwidth across different traffic patterns. Thus, we propose a memory-centric network in which all processor channels are connected to HMCs and not to any other processors as all communication between processors goes through intermediate HMCs. Since there are multiple HMCs per processor, we propose a distributor-based network to reduce the network diameter and achieve lower latency while properly distributing the bandwidth across different routers and providing path diversity. Memory-centric networks lead to some challenges including higher processor-to-processor latency and the need to properly exploit the path diversity. We propose a pass-through microarchitecture, which, in combination with the proper intra-HMC organization, reduces the zero-load latency while exploiting adaptive (and non-minimal) routing to load-balance across different channels. Our results show that memory-centric networks can efficiently utilize processor bandwidth for different traffic patterns and achieve higher performance by providing higher memory bandwidth and lower latency.

Emerging power-supply-on-chip applications such as on-chip DC-DC conversion, energy harvesting, and LED drivers use switching regulator ICs integrated with digital controllers. Although the resulting mixed-signal systems call for efficient system-level behavioral simulation, this remains difficult due to the fast switching and slow transients of the regulator and the high complexity of the controller. This paper presents a truly event-driven approach for modeling and simulating such integrated power systems entirely in SystemVerilog. By modeling various switching regulator topologies as switched linear networks whose responses can be expressed as a sum of complex exponentials, ctm-1e--atu(t), the accurate voltage/current waveforms can be captured by updating the coefficients, c, at each input or switching event. The model is applied to two examples, a power factor corrector and switched-capacitor DC-DC converter, and the results demonstrate that the proposed simulator can achieve 20~100× improvements in speed while maintaining SPICE-level accuracy in evaluating power efficiency, steady-state ripples, and power factor.

With rapid developments in virtual reality (VR), haptics, communications technology and digital multimedia, there has been increasing demand for creation and widespread development of more realistic or immersive display systems. Consumers are eager to experience engrossing contents capable of providing presence, beyond traditional audio-visual media. In response to this demand, tactile and haptic interaction is also becoming increasingly important. Recently, MPEG-V standard (ISO/IEC 23005) has been published. The MPEG-V provides architecture and metadata for interaction and interoperability between virtual worlds and real worlds through various sensors and actuators. The aim of this paper is to provide an overview of MPEG-V standard, particularly regarding haptic and tactile interactions.

This paper describes a simulation-based approach to establish whether a ring-oscillator always converges to the correct mode of operation regardless of its initial conditions and variability conditions. The verification is performed using a predictive global optimization algorithm that looks for a problematic initial state from a discretized state space. The algorithm explores the initial states that can maximize the settling time for the oscillator to reach its final steady state. If any of these initial states visited during the search is found exhibiting false oscillation behaviors for certain variability conditions, the initial state is reported as problematic. On the other hand, if the initial state with the globally maximum settling time is found without discovering such problematic states, the oscillator is reported free of start-up failures. It can be shown that despite the finite number of initial state candidates considered and finite number of Monte-Carlo samples to model variability, the proposed algorithm can verify the oscillator to a prescribed confidence level. Demonstrated on various even-stage differential ring oscillators, the algorithm was able to validate the circuit for 99% yield with 99.9% confidence level by evaluating 7~60 initial states each with 1,000 Monte-Carlo samples. To our knowledge, this is the first algorithm ever reported to address start-up failures with variability.

In many applications, mass-produced chips need to be tagged with individual identification numbers (i.e. chip ID). One way to do this without requiring post-fabrication programming steps is to generate the unique ID per chip exploiting random device mismatch. However, it can be prone to mis-identification due to time-varying noise that may cause a different ID to be read from the same chip each time. This paper presents a wide-aperture, low-noise clocked comparator design and a novel ID detection scheme based on maximum likelihoods (ML) that can significantly reduce the probability of mis-identification for such random chip ID generators. A prototype chip fabricated in 0.18-μm CMOS demonstrates the measured input-referred noise of the comparator as low as 265-μVrms, while preserving the wide input-referred offset distribution of 22-mVrms. As for the detection scheme, the analysis shows that when detecting 1024 unique IDs, the proposed ML detection scheme can achieve the mis-identification rate of 1.73×10-18with 64-bits while the previous scheme based on Hamming distances (HD) would require 90-bits.

This paper proposes the use of discrete optimization techniques for variability-aware analog circuit synthesis. Starting from an observation that the continuous design space of analog circuits can be effectively covered by a finite number of discrete points in presence of variations, new algorithms are explored to address three aspects of discrete optimization: discretizing a continuous design space, selecting candidate points on the discretized grid, and comparing the statistical measures between multiple candidate points. A digitally-controlled oscillator (DCO) example demonstrates that the proposed optimization technique can efficiently find the design that balances between the resolution, linearity, phase noise, and power dissipation.

A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to the increasing interaction between the analog and digital circuits. Once the functionality of the system model is verified, the model can be leveraged as the specification for generating and validating the circuit and physical implementations of the system, automating a large portion of the design process.

This paper proposes two practical approaches to address global convergence failures, commonly encountered in mixed-signal systems in which analog and digital components closely interact. That is, a nominally-working system may fail intermittently depending on its initial conditions upon start-up. The first approach uses a data clustering analysis and verifies global convergence with randomly-selected pilot simulations. The second approach adopts the practice of representing indeterminate states with X by defining its equivalent concept for analog based on entropy. With oscillator and phase-locked loop examples, it is demonstrated that the proposed approaches can effectively detect the failures and guide designers where to add more resets to prevent them.

This paper presents an approach to generate test vectors to characterize analog/mixed-signal circuits and its application to check the correspondence between a circuit and its HDL functional model. Interestingly, the abstract behavior of most analog circuits is a linear system, but sometimes only when viewed through a transformation of variables. When linearity holds, validation for the consistency between a circuit and a model can be efficiently performed with a small set of test vectors that grows linearly with the number of analog inputs. The linear abstraction for analog circuits also helps us distinguish different types of analog and digital I/O ports and verify their consistency effectively. We demonstrate the implemented tool by comparing a simple serial link receiver against its functional model.

This paper proposes a circuit optimization approach that can ease the computational burden on the simulation-based circuit optimizers by leveraging simple design equations that reflect the designer's intent. The technique is inspired by continuation methods (a.k.a. homotopy) in numerical analysis where a hard problem is solved by constructing an easier problem first and gradually refining its solution to that of the hard problem. In a circuit optimization context, the designer's simplified equations for the circuit serve as the easier problem. These simplified design equations are easy to write as they need not be completely accurate and have intuitive, well-understood solutions. Nonetheless, in several circuit examples, it was found that the designer's equations serve as better guidance than the conventional, fixed-point equations. As a result, the proposed approach demonstrates the better convergence to the desired solution with less computational efforts.

This paper demonstrates that the steady-state and adjoint sensitivity analyses can be extended to stochastic mixed-signal systems based on Markov chain models. The examples of such systems include digital phase-locked loops and delta-sigma data converters, of which steady-state response is statistical in nature, consisting of an ensemble of waveforms with probability distribution. For efficient Markov-chain analysis, the paper describes three methods that can limit the number of states: a state discretization scheme based on Gaussian decomposition, a state exploration algorithm that discovers the recurrent states, and a state truncation algorithm that eliminates the states with negligible stationary probabilities. The stochastic AC analysis is performed by deriving a first-order ordinary differential equation governing the perturbations in the stationary probabilities and solving it via phasor analysis. In the digital PLL and first-order ΔΣ ADC examples, the number of states was reduced by a factor of 35 and the frequency-domain phase and noise transfer functions were simulated with a 57~22,000x speed-up compared to using transient, Monte-Carlo simulations.

This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that the generalized ISF is a subset of a time-varying impulse response, the ISF is efficiently computed based on periodic time-varying system analysis techniques. Compared to the previous ISF characterization method based on transient simulations, a speed-up of ~5times is achieved.

This paper describes a noise-based method of estimating the effects of device random mismatch on circuit's transient response, such as delay and frequency. The proposed method models DC mismatch as equivalent AC pseudo-noise and exploits the fast periodic noise analysis (PNOISE) available in RF circuit simulators to compute the resulting variation in the circuit response. While the method relies on Gaussian mismatch distributions and linear perturbation model, it can model and analyze correlations as well as identify the most sensitive design parameter to mismatches with no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of 100--1000x compared to a 1000-point Monte-Carlo method.

This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commercial RF simulators, the circuit's linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage-domain models, instead of being modeled as strongly-nonlinear systems directly.

A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13μm CMOS, the area is 0.182mm2 and the supply is 1.5V.