The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target for high-performance computing (HPC) systems, a 25-high-$Q$-factor (300 MHz), 150-$\mu \text{m}$-thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57-$\mu \text{m} V_{\mathrm {DD}}$-bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10-$\mu \text{m}$-horizontal-pitch nano- through-silicon via ($n$TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency$\eta \,\,=83$% can be obtained for 1-$\mathrm {W}/{\mathrm {mm}}^{2}$power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively.

We present a$\mu \text{m}$-thin-profile power delivery solution including a charge pump with integrated passives. Targeting 1 W/mm2or higher power density, a 2.5-D high-density metal-insulator-metal (MIM) capacitor deposited on high aspect ratio (HAR) (up to 5) oxide studs is proposed. With approximately 25-nm-thick HfAlOx dielectric, its measured capacitance density is 25.4 nF/mm2for a capacitor size ranging from 1/16 mm2to 1 mm2. This shows$3.6\times $density improvement compared with the planar MIM. Theoretically, 86 nF/[email protected] bias can be obtained if a 10-nm dielectric is deposited. Moreover, the measured leakage current density is within 65 pA/mm2at 1-V bias (negligible for a 1 W/mm2-power delivery). For a backside (BS) power delivery, this 2.5-D MIM capacitor can be realized by only three BS metal layers. This enables the low-cost and thin-profile delivery system ($\sim \!\!\mu \text{m}$thickness), and the whole power delivery efficiency including a 1/2-ratio charge pump is$\eta \,\,=84$%@1 W/mm2(>5% boost in the power efficiency).

Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all system, technology and implementation level options brought with these features, the design space increases to an extent where traditional 2D tools cannot be used any more for efficient exploration. Therefore, the cost-effective design of future 3D ICs products will require new planning and co-optimisation techniques and tools that are fast and accurate enough to cope with these challenges. In this paper we present design methodology and the practical EDA tool chain that covers different aspects of the design flow and is specific to efficient design of 3D-ICs. Flow features include: fast synthesis and 3D design partitioning at gate level, TSV/micro-bump array planning, 3D floor planning, placement and routing, congestion analysis, fast thermal and mechanical modeling, easy technology vs. implementation trade-off analysis, 3D device models generations and Design-for-Test (DfT). The application of the tool chain is illustrated using concrete example of a real-world design, showing not only the applicability of the tool chain, but also the benefits of heterogeneous 2.5 and 3D integration technologies.

Three dimensional integration complements semiconductor scaling; it enables a higher integration density as well as heterogeneous technology integration. Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimize system performance.

We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via's (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.

3D-Stacked ICs (3D-SIC) based on Through-Silicon Vias (TSVs) offer alleviation of the performance and interconnect density bottlenecks faced by traditional CMOS scaling. As a result there is a lot of industrial focus to make this technology available for the next generation of SoCs. However, for 3D integration to become a viable product approach, it requires that the additional processing steps necessary preserve the integrity of both front-end and back-end of devices and constituting materials. 3D processing steps such as TSV insertion and wafer thinning, have an impact on the functionality and performance of analog and digital circuits, which needs to be accounted for during the design phase. Moreover, testing 3D-SICs calls for more complex test flow trade-offs and enhanced design-for-test architectures for test access within the stack. Finally, the reliability consequences with respect to thermal and mechanical stress in dense stacks of thinned wafers need to be carefully assessed to guarantee a target product life time. In this presentation we discuss the above mentioned challenges and some of the emerging solutions.

Substrate noise problems in a system-on-a-chip hamper the smooth cohabitation between analog and digital circuitries on the same die. Solving those problems will shorten the time to market. This paper presents a methodology that gives designers the necessary insight to solve this substrate noise problem. The methodology combines the strengths of the electromagnetic simulator, the parasitic extractor, and the circuit simulator. Its main assets are the ease of use, an acceptable simulation time, and a good accuracy. Moreover, this methodology does not need doping profiles that are hard to get hold off. The proposed methodology is demonstrated on two challenging examples: a 48-53-GHz LC voltage-controlled oscillator and a dc-to-5-GHz wideband receiver designed, respectively, in a 0.13-mum and a 90-nm CMOS technology. The substrate noise coupling mechanisms are revealed for both examples in a simulation time of less than 2 hours. The methodology is successfully validated by measurements performed on real-life prototypes of those examples with an accuracy of 1-2 dB.

This paper addresses system-level design of time- interleaved analog-to-digital converters (TI-ADCs) for ultra-wide band communications. Design space exploration of a TI successive approximation architecture is performed via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing the main ADC blocks in a 90-nm 1-V CMOS technology. Different speed/resolution scenarios are efficiently investigated and the impact of parallelism on system performance, yield and power consumption is assessed starting from the early design phases, finally enabling the selection of two candidate implementations (a 6-bit 4.6- mW and a 7-bit 8.1-mW ADC targeting 1 GS/s) that effectively trade accuracy for energy efficiency and area.

In this paper we present a macromodeling methodology to accurately reproduce the timing and the peak/average power behaviors of digital standard cells for a wide range of operating conditions determined by the load, the input transition time, and the supply variations. Our methodology significantly reduces the number of transient simulations for the cell characterization. The numerical results for the transient simulation of large digital systems indicate that we achieve a mean error of 10% for the power consumption and 4% for the propagation delay of the complete digital system while the mean error for the used gates in this system is 2.5% when compared to SPICE-based simulations.

We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-/spl mu/m CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures include 5.8GHz effective resolution bandwidth and 0.8pJ/conversion-step at 1-GS/s and Nyquist conditions.

In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less substrate-noise generation in large digital systems. It proposes a technique to assign combinatorial cells and flip-flops to the clock regions. It also takes into account the impact of unintentional clock skew such as jitter on the computed skews in order to assure a robust design. During the optimization, it uses compressed supply-current profiles to improve the CPU time. Experimental results show more than a factor-of-2 reduction in substrate-noise generation from large digital circuits of which the skews are optimized

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.

The paper reports a novel simulation methodology for the analysis and prediction of substrate noise impact on analog/RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism. This methodology allows investigation of the role of the separate devices (also parasitic devices) in the analog/RF circuit in the overall impact. In this way, it is revealed which devices have to be taken care of (shielding, topology change) to protect the circuit against substrate noise. The developed methodology is used to analyze the impact of substrate noise on a 3 GHz LC-tank voltage controlled oscillator (VCO) designed in a high-ohmic 0.18 /spl mu/m 1 PM6 CMOS technology. For this VCO (in the investigated frequency range from DC to 15 MHz) impact is mainly caused by resistive coupling of noise from the substrate to the non-ideal on-chip ground interconnect, resulting in analog ground bounce and frequency modulation. Hence, the presented test-case reveals the important role of the on-chip interconnect in the phenomenon of substrate noise impact.

In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..

The digital switching noise that propagates through the chip substrate to the analogue circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock; and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reductions in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.

A methodology is presented for the physical design automation of array-type analog blocks such as encountered in high-speed data converters and other analog circuits. The approach takes into consideration typical analog constraints and offers full flexibility. A three-step procedure (floorplanning, symbolic routing, and technology mapping), of which the last two steps have been automated in a tool called Mondriaan, solves the layout synthesis problem in a fast and technology-independent way. A set of bus and tree device generators complements the tool set. Industrial-strength examples prove that the proposed solution speeds up the generation of high-quality analog layouts significantly.

This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5µm CMOS technology, which has been designed using a systematic design methodology for current-steering D/A converters. A flexible architecture is proposed for which the design parameters are calculated using a performance-driven top-down design methodology. The layout of the regular structure typical for D/A converters is automatically generated. Measurement results are reported. Due to the systematic design methodology, the design was realized in less than one month total accumulated person effort.

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specified by the user and determines optimal test signals that maximize the detectability of all faults. As statistical fluctuations have to be considered when evaluating analog circuits, it is based on a statistical test criterion. Two examples demonstrate the practical use and versatility of this approach.