The T-coil circuit is finding new life on-chip in wideband circuits. Its design remains shrouded in myth, with complicated design equations whose derivations can be very involved. There is almost no intuition to guide its user. We show that the symmetrical T-coil is actually an equivalent of the classic lattice network. Using the Brune equivalent of the lattice and the bisection theorem, the apparent complexity dissolves and insights follow. All transfer functions can be derived in one or two steps, and it becomes clear why driving a capacitor load through the symmetrical T-coil gives twice the bandwidth of inductive peaking. Some insights extend to the asymmetrical T-coil circuit.

A design-oriented analysis of a transimpedance amplifier (TIA) reveals the optimum compression-free dynamic range for downconverted blockers lying in its 2nd-order transition band. The unique circuit topology is chosen to eliminate low-frequency zeros of the transfer function to TIA output with only one OpAmp. Two approaches lead to TIA designs with or without capacitive positive feedback. Both configurations are analyzed and discussed. Simple and accurate design equations allow the component value to be selected straightforwardly.$\omega _{0}$and$Q$of the two poles are independently controlled. Analytical expressions for out-of-band (OOB) linearity are derived, explaining different distortion mechanisms from both gate and drain voltages of a FET. The FET gate voltage is shown to affect the distortion even if its swing is much lower than the drain voltage swing. The design fully benefits from 2nd-order filtering, yielding optimum blocker tolerance. Power dissipation is limited by the requirements for noise figure and independent pole control. A mixer-first receiver that operates from 1 to 7GHz is realized on 65nm RF-SOI CMOS. It displays +31.1dBm OOB input-referred third-order intercept point (OOB-IIP3), and +11.8dBm OOB blocker 1-dB compression point (B1dB). The TIA consumes 22mW. The prototype verifies the TIA design.

We develop an approximate frequency-independent equivalent circuit for integrated inductors on semiconducting substrates. All values of LCR in the equivalent circuit can be calculated directly from inductor geometry. The equivalent circuit captures: the skin effect, the proximity effect, the substrate capacitive loss, and the distributed capacitance. With careful definition of inductor quality factor, we are able to calculate the contribution of substrate capacitive loss and benefits of a substrate shield. Our model was put to test by successfully predicting the published quality factors of various inductors and proving that their geometries are close to optimum.

The great importance of power consciousness is well understood in mobile wireless communications. However, with growing experience the fundamental principles underlying power conscious design of RF circuits, systems, and networks are only now becoming known. Using as example ultralow-power wireless devices for messaging such as paging receivers and wireless sensor networks, the first part of this paper presents the relationship between current consumption and dynamic range of low-noise amplifiers, mixers, oscillators, and active filters. The second part of the paper covers issues of modulation, protocols, and networking that would be required in dense networks of wireless sensors, which communicate using very little energy. These ideas are expected to find use in most forms of digital wireless communications.

Article Free Access Share on Low power RF integrated circuits: principles and practice Authors: A. A. Abidi Electrical Engineering Department, University of California, Los Angeles, CA Electrical Engineering Department, University of California, Los Angeles, CAView Profile , H. Darabi Electrical Engineering Department, University of California, Los Angeles, CA Electrical Engineering Department, University of California, Los Angeles, CAView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 1–6https://doi.org/10.1145/313817.313824Published:17 August 1999Publication History 4citation733DownloadsMetricsTotal Citations4Total Downloads733Last 12 Months19Last 6 weeks6 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper describes the simulation and layout techniques used and developed in the design of a single-chip CMOS 900 MHz spread-spectrum wireless transceiver:

A new read channel architecture is proposed, which uses EPR4 pre-equalization to simplify the hardware required in an all-analog circuit implementation of an FDTS /spl tau/=2 detector and its associated timing recovery. The main concept is that by transforming the channel characteristics into an EPR4 target, the FIR filters required in the DFE need only be a few taps long, and the clock may be recovered from the EPR4 pre-equalized data before it enters the DFE. The FDTS /spl tau/=2 performance is obtained from a /spl tau/=1 implementation, accompanied by an error-pattern identifier. This architecture is designed for high-rate MTR codes, when it outperforms an EPR4 ML read channel at user densities of PW50/T=2 or greater.

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personal communications bands are surveyed. It is seen from this that when ICs enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receivers, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-ICs to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for ICs for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simplified radio architectures, all-CMOS radios appear promising in the 900 MHz to 2 GHz bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example.>

The authors describe the implementation and performance of what might be termed a 'Vector A/D Converter'. The IC stores a codebook of vectors on-chip, accepts a 16-element analog vector at the input, calculates the Euclidean distance between the input and all codevectors (referred to as global search), and outputs an 8-bit code to index the codevector closest to the input prompt. At a 5 MHz clock rate it dissipates less than 50 mW to quantize 16 element analog vectors once every 10 clock periods, giving a 30 Hz frame rate for a 512*512 pixel gray scale image.>

A table-based approach to the empirical modeling off FETs in circuit simulators addresses the specific requirements of analog circuit design, such as accuracy in reproducing small-signal parameters, large signal nonlinearities, subthreshold characteristics, substrate effects, short-channel effects, and voltage dependent capacitances. Efficiencies in storage and computation brought about by this model in SPICE considerably speed up circuit simulation, compared to an analytical model offering similar accuracy. Methods are described to extract the table entries. The model is not specific to any one type of device or technology, although examples are given of how it may be simplified by using physical insights into device operation.>

A four-pole continuous-time equalizer has been developed to minimize the error rate in rigid-disk magnetic storage channels employing peak detection at high recording densities. The design process consisted of two parts. A nominal model of the disk drive characteristics in the time and frequency domains was obtained from digitized waveforms at the output of a read-head amplifier in a disk drive system. The relative performance of candidate equalizers was studied by subjecting them to the measured data waveforms and then either estimating or measuring the resulting bit error rate in a simulated peak detector, operating on the equalized waveforms. The equalizer outperforms more complex structures proposed for this task and is well suited for implementation as an analog CMOS active filter with low power dissipation. Its constellation of four poles and a zero appears to be useful for several types of magnetic media.>