Demo Data from EDBT 2026 / reviewers in the wild / expert
Daniel Shumow
dblp:24/7481 · also Dan Shumow
· DBLP profile ↗
7ranked-venue papers
1as first author
2since 2021 · last 2024
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 5 · 1 since 2021Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
4 papers |
Authentication and access control · 46% Cryptographic primitives and cryptanalysis · 31% Network security · 14% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 4 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Authentication and access control › authentication
authentication protocols |
0.8 | 1 | 2024 | RADIUS/UDP Considered Harmful · USENIX Security Symposium 2024 |
Cryptographic primitives and cryptanalysis
pseudorandom generators |
0.4 | 1 | 2019 | An Analysis of NIST SP 800-90A · EUROCRYPT (2) 2019 |
Network security › protocol security
protocol vulnerabilities |
0.2 | 1 | 2024 | RADIUS/UDP Considered Harmful · USENIX Security Symposium 2024 |
Cryptographic primitives and cryptanalysis › hash functions › dedicated hash functions
SHA-1 |
0.1 | 1 | 2017 | Speeding up detection of SHA-1 collision attacks using unavoidable attack conditions · USENIX Security Symposium 2017 |
Methods — techniques the papers use, named apart from their topics
microarchitectural simulation · 0.3cryptographic analysis · 0.3collision attack optimization · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | RADIUS/UDP Considered Harmful
Sharon Goldberg, Miro Haller, Nadia Heninger, Mike Milano, Daniel Shumow, Marc Stevens 0001, Adam Suhl |
USENIX Security Symposium | 5 |
| 2023 | Incorrectly Generated RSA Keys: How I Learned To Stop Worrying And Recover Lost PlaintextsabstractAbstract When generating primes $p$ and $q$ for an RSA key, the algorithm specifies that if $p-1$ and $q-1$ must be relatively prime to the public exponent $e$. If this is not done, then the decryption exponent is not well defined. However, what if a software bug allows the generation of public parameters $N$ and $e$ of an RSA key with this property and then it is subsequently used for encryption? Though this may seem like a purely academic question, a software bug in a preview release of the Windows 10 operating system makes this question of more than purely theoretical. Without a well defined decryption exponent, plaintexts encrypted to such keys will be undecryptable thus potentially losing user data, a serious software defect. Though the decryption exponent is no longer well defined, it is in fact possible to recover the a small number of potential plaintexts, if the prime factors $p$ and $q$ of the public modulus $N$ are known. This paper presents an analysis of what steps fail in the RSA algorithm and derives a plaintext recovery algorithm. The runtime of this algorithm is $O(e)$ making it practical to use, and it has been implemented in python. Daniel Shumow |
Comput. J. | 1 |
| 2019 | An Analysis of NIST SP 800-90A
Joanne Woodage, Daniel Shumow |
EUROCRYPT (2) | 2 |
| 2017 | Speeding up detection of SHA-1 collision attacks using unavoidable attack conditions
Marc Stevens 0001, Daniel Shumow |
USENIX Security Symposium | 2 |
| 2013 | Montgomery Multiplication Using Vector Instructions
Joppe W. Bos, Peter L. Montgomery, Daniel Shumow, Gregory M. Zaverucha |
Selected Areas in Cryptography | 3 |
| 2012 | Inspection resistant memory: Architectural support for security from physical examinationabstractThe ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after the power has been cut. These effects cannot be hidden easily, and if the secret stored on chip is of sufficient value, an attacker may go to extraordinary means to learn even a few bits of that information. Solving this problem requires a new class of architectures that measurably increase the difficulty of physical analysis. In this paper we take a first step towards this goal by focusing on one of the backbones of any hardware system: on-chip memory. We examine the relationship between security, area, and efficiency in these architectures, and quantitatively examine the resulting systems through cryptographic analysis and microarchitectural impact. In the end, we are able to find an efficient scheme in which, even if an adversary is able to inspect the value of a stored bit with a probabilistic error of only 5%, our system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999% probability. Jonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Daniel Shumow, Vinod Vaikuntanathan, Timothy Sherwood |
ISCA | 5 |
| 2012 | Affine Pairings on ARM
Tolga Acar, Kristin E. Lauter, Michael Naehrig, Daniel Shumow |
Pairing | 4 |