Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Nicholas C. Doyle

dblp:24/7549 · DBLP profile ↗
← Back
3ranked-venue papers
2as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 79% Reconfigurable computing and FPGAs · 14% Processor architecture and microarchitecture · 7%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache design		 0.212015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Memory systems › cache management
cache replacement		 0.212015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Memory systems › cache › CPU cache
l1 data cache		 0.212015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Memory systems
cache coherence		 0.112015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Processor architecture and microarchitecture
chip multiprocessor		 0.112015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Reconfigurable computing and FPGAs › FPGA SoC
FPGA-based multicore system		 0.112015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015
Reconfigurable computing and FPGAs › FPGA-based processor implementation
soft-core processor		 0.112015
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems · FPGA 2015

Methods — techniques the papers use, named apart from their topics

design space exploration · 0.2
YearPublicationVenuePosition
2017 Performance impacts and limitations of hardware memory access trace collection
abstract
In today's multicore architectures, complex interactions between applications in the memory system can have a significant and highly variable impact on application execution time. System designers typically use hardware counters to profile execution behaviours and diagnose performance problems. However, hardware counters are not always sufficient and some problems are best identified with full memory access traces. Collecting these traces in software is very expensive; our work explores using dedicated hardware for memory-access trace collection. We analyze the limitations of this approach and its impacts on application performance. Our study is performed on actual hardware using two very different CPU platforms: 1) the PolyBlaze multicore soft processor and 2) the ARM Cortex-A9. In both cases, the data collection is implemented on an FPGA. Using micro-benchmarks designed to test the bounds of memory access behaviour, we illustrate the operational regions of data collection and the impact on system performance. By examining the bandwidth bottlenecks that limit the rate of data collection, as well as hardware architecture choices that can aggravate the impact on application performance, we provide guidelines that can be used to extrapolate our analysis to other systems and processor architectures.
Nicholas C. Doyle, Eric Matthews, Graham M. Holland, Alexandra Fedorova, Lesley Shannon
 DATE1
2015 Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems
abstract
Combining multi-processing with the high level of configurability possible with FPGA-based soft-processors, this paper presents a multiprocessing framework based on the MicroBlaze soft-processor that provides multicore support and fully coherent, independently configurable Level 1 Caches with Linux multicore support. This architecture allows for fine-grain configurability of the system, allowing for FPGA resources to be better optimized for a specific embedded application. We use our framework to explore the L1 Data Cache configuration, developing a metric for efficiency based on resource usage and static application runtime. We find that a Pseudo-Random replacement policy is consistently the more efficient choice for FPGA systems.
Eric Matthews, Nicholas C. Doyle, Lesley Shannon
 FPGA2
2013 Complete architecture and demonstration design for a new combined WiMAX/DSRC system with improved vehicular networking efficiency
Nicholas C. Doyle, Nabih Jaber, Kemal Ertugrul Tepe
 Ad Hoc Networks1