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Jens Krueger

dblp:24/7583 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 38% Energy-efficient computing · 38% High-performance computing · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
energy-efficient architecture
0.112011
Hardware/software co-design for energy-efficient seismic modeling · SC 2011
High-performance computing
scientific computing systems
0.012011
Hardware/software co-design for energy-efficient seismic modeling · SC 2011
High-performance computing › scientific computing systems
seismic imaging
0.012011
Hardware/software co-design for energy-efficient seismic modeling · SC 2011

Methods — techniques the papers use, named apart from their topics

performance and power modeling · 0.1FPGA-accelerated architectural simulation · 0.1
YearPublicationVenuePosition
2011 Hardware/software co-design for energy-efficient seismic modeling
abstract
Reverse Time Migration (RTM) has become the standard for high-quality imaging in the seismic industry. RTM relies on PDE solutions using stencils that are 8th order or larger, which require large-scale HPC clusters to meet the computational demands. However, the rising power consumption of conventional cluster technology has prompted investigation of architectural alternatives that offer higher computational efficiency. In this work, we compare the performance and energy efficiency of three architectural alternatives -- the Intel Nehalem X5530 multicore processor, the NVIDIA Tesla C2050 GPU, and a general-purpose manycore chip design optimized for high-order wave equations called "Green Wave." We have developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design. Results show that across highly-tuned high-order RTM stencils, the Green Wave implementation can offer up to 8x and 3.5x energy efficiency improvement per node respectively, compared with the Nehalem and GPU platforms. These results point to the enormous potential energy advantages of our hardware/software co-design methodology.
Jens Krueger, David Donofrio, John Shalf, Marghoob Mohiyuddin, Samuel Williams 0001, Leonid Oliker, Franz-Josef Pfreundt
SC1