Demo Data from EDBT 2026 / reviewers in the wild / expert
Georgios Glykopoulos
dblp:24/763
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Internet architecture and protocols · 50% Routing and switching · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Routing and switching › packet switching
cell switching |
0.0 | 1 | 2001 | Wormhole IP over (connectionless) ATM · IEEE/ACM Trans. Netw. 2001 |
Internet architecture and protocols › ATM networks
IP over ATM |
0.0 | 1 | 2001 | Wormhole IP over (connectionless) ATM · IEEE/ACM Trans. Netw. 2001 |
Reconfigurable computing and FPGAs
FPGA prototyping |
0.0 | 1 | 2001 | Wormhole IP over (connectionless) ATM · IEEE/ACM Trans. Netw. 2001 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | Wormhole IP over (connectionless) ATMabstractHigh-speed switches and routers internally operate using fixed-size cells or segments; variable-size packets are segmented and later reassembled. Connectionless ATM was proposed to quickly carry IP packets segmented into cells (AAL5) using a number of hardware-managed ATM VCs. We show that this is analogous to wormhole routing. We modify this architecture to make it applicable to existing ATM equipment: we propose a low-cost, single-input, single-output wormhole IP router that functions as a VP/VC translation filter between ATM subnetworks. When compared to IP routers, the proposed architecture features simpler hardware and lower latency. When compared to software-based IP-over-ATM techniques, the new architecture avoids the overheads of a large number of labels, or the delays of establishing new flows in software after the first few packets have suffered considerable latencies. We simulated a wormhole IP routing filter, showing that a few tens of hardware-managed VCs per outgoing VP usually suffice. We built and successfully tested a prototype, operating at 2/spl times/155 Mb/s, using one field programmable gate array (FPGA) and DRAM. Simple analysis shows that operation at 10 Gb/s and beyond is feasible today. Manolis Katevenis, Iakovos Mavroidis, Georgios Sapountzis, Evangelia Kalyvianaki, Ioannis Mavroidis, Georgios Glykopoulos |
IEEE/ACM Trans. Netw. | 6 |