This paper proposes an inductorless wideband common-gate (CG)-common-source (CS) noise-cancelling (NC) low-noise amplifier (LNA) with current reuse (CR) for ultra-low voltage (ULV) application. In the conventional NC LNA with CR, to reuse the DC current of the auxiliary amplifier, three transistors are stacked in a single branch, leading to a reduced voltage headroom. Moreover, additional inductor and capacitors are required, resulting in a large silicon area. In the proposed work, the DC current of the auxiliary amplifier can be reused without using any inductor. Meanwhile, only two transistors are stacked in a single branch, making it suitable for ULV application. Fabricated in 28 nm CMOS, this work exhibits a voltage gain of 20 dB with a 3-dB bandwidth of 0.2 to 2.85 GHz, a minimum NF of 2.9 dB at 1.7 GHz and an IIP3 of -12.3 dBm at 1 GHz. It consumes 1.74 mW from a 0.6 V supply and occupies a very compact die area of 0.0048 mm2.

In designing a mm-wave ultra-wideband pulse-Doppler radar IC, one of the main challenges encountered is to reduce the high power consumption of the circuitries in the IC. A direct-RF receiver can be used in the radar’s design to reduce the radar’s power consumption. However, a digitizer that can directly digitize mm-wave ultra-wideband radar pulses is needed to implement such a receiver. This work presents the design of such a digitizer, which comprises several multi-pass sub-ADCs that operate together. Each multi-pass sub-ADC works fundamentally like a flash ADC but comprises one comparator only. A test chip containing a 6-bit prototype of the digitizer is fabricated in a 40 nm CMOS technology. The prototype consumes 19.7 mW when operated at 4 GSa/s and can operate with input signal frequencies of up to 64 GHz while achieving a −1.7/−6 dBFSSNDRof 21.1/22.8 dB at 60 GHz (the correspondingFoMis 532/434 fJ/c-s). The digitizer has a relatively high effective parallel-equivalent input impedance at 60 GHz, which, in a radar IC implementation, allows it to be driven with a relatively low power-consuming 60 GHz RF buffer. These are achieved without the digitizer being fabricated in a much more advanced technology node.

This paper reports a cross-coupled pair regeneration based programmable gain amplifier (CCPR- PGA) with an improved total harmonic distortion (THD) performance. By utilizing the ping-pong technique, two identical conventional CCPR-PGAs are operating alternatively. These two CCPR-PGAs connect to the output of the overall PGA only at their hold state, as a result, the ripples generated during the processes of reset, sample and regeneration are effectively suppressed. Simulated in 28-nm CMOS technology, the proposed PGA achieves a gain range of 45.4 dB with a gain error of ± 0.3 dB. The bandwidth of the proposed PGA reaches 40 MHz with a clock frequency of 100 MHz. Moreover, the THD performance is improved by 25.8 dB at 1 MHz and 17.6 dB at 10 MHz when compared to the conventional structure. The overall PGA consumes 460 μA current from a supply voltage of 0.9 V.

The recent development of wafer-level, low-cost packaging platforms based on the silicon interposer and direct wafer bonding has paved a new way toward high-performance millimeter-wave to terahertz 2.5/3D heterogeneous integration, enabling high-speed wireless communication and chip-to-chip interconnects. Using this emerging technology, several passive components are studied in this paper toward the terahertz applications. One 240 GHz distributed mushroom antenna is designed using interposers to form multiple resonances unit- cell, achieving 7.16 dBi gain with 76% radiation efficiency. A 300 GHz differential patch antenna is designed, delivering 5.6 dBi gain with 88% radiation efficiency. A 60 GHz directional coupler based on interleaving topology is proposed and simulated, showing a 3.3 dB coupling factor with more than 30 GHz bandwidth. These preliminary results reveal a promising solution by using the wafer-to-wafer packaging platform to build high-performance passive building blocks.

This paper presents a 2.4-6 GHz highly integrated broadband GaN power amplifier (PA) with three stages for 2.4-/5-GHz dual-band 802.11ax application. A compact external output matching network is introduced to realize broadband output matching, while reducing the loss of the output matching network and saving the chip area. A novel topology of coupled resonators is exploited for the broadband inter-stage matching to cover the 802.11ax bands from 2.4 to 6 GHz. In the proposed topology, the coupling between the primary and secondary resonators is through a series inductor and a series capacitor. Compared with other conventional coupled resonators, the proposed topology produces an additional complex pole, further extending the bandwidth. The PA was designed and fabricated in Wolfspeed 0.25- μm GaN-on-SiC technology. The implemented PA achieves a saturated output power (Psat) of 35.2-36.3 dBm with a maximum power added efficiency (PAE) of 38-53% from 2.4 to 6 GHz. When tested with an 80-MHz, 256-quadratic-amplitude modulation (QAM) 802.11ax signal, the PA delivers an average output power of 27.1 and 25.7-27.2 dBm with a PAE of 20.9% and 18.4-24.6% in the 2.4-GHz and 5-GHz wireless local area network (WLAN) bands, respectively, while meeting the specification of error vector magnitude (EVM) below -32 dB.

This brief presents a bidirectional nonlinearly coupled quadrature voltage-controlled oscillator (BNC-QVCO) incorporating passive phase interpolation for the generation of multiphase signals. In addition, to generate multiphase signals, the proposed bidirectional nonlinearly coupling network improves the phase noise performance of the QVCO by producing approximate-in-phase injection-coupling currents into the LC tank. Moreover, to balance the amplitude of eight-phase signals, an additional passive amplitude division circuit is implemented with capacitor banks for calibration. For verification, a BNC-QVCO incorporating passive phase interpolation is implemented in a 40-nm CMOS technology with a core area of 0.13 mm2. The measured multiphase signals achieve a phase noise of -116.57 dBc/Hz at 1-MHz offset from 4.32 GHz. The power consumption without buffers is 10.2 mW under 1-V supply voltage and a 20% frequency tuning range from 4 to 4.8 GHz is achieved with the implemented digitally controlled capacitor banks.

This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calibration has been implemented to overcome conversion gain variation due to process-voltage-temperature (PVT) variation. The post-layout simulation results show that the SFDR/-THD of the proposed VTC reaches 58.7dB/56.3dB at 3GS/s near Nyquist (typical corner). The VTC achieves 144ps output range with 0.83mW power consumption at 3GHz. It occupies an active area of 41.3um × 34.4um implemented in 65nm CMOS.

Using on-chip slow-wave transmission line (SW-TL) has paved a new way towards millimeter-wave (mm-wave) to terahertz (THz) low power and high speed inter-/intra-chip communications. This work presents an on-chip SW-TL featured by periodic comb-shape grooves with capability to strongly localize electric-field. A gradient groove structure is proposed to serve as the mode converter and performs the mode transformation between the quasi-TEM wave and the slow-wave with low return loss. Due to field confinement, when two SW-TL are only 2.4 μm apart, more than 19 dB crosstalk suppression is observed compared with two conventional TL with the same metal spacing. A dual-channel 160 GHz frequency-shift keying (FSK) transceiver is designed in 65 nm CMOS technology. The preliminary results show that by exploiting SW-TL as the silicon channel, the receiver can recover error-free 4 Gb/s dual-channel data, whereas the eye diagram of the transceiver using traditional transmission line (TL) is fully distorted. The transceiver consumes 36 mW DC power from a 1.2 V power supply.

This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inverter chain is deployed as the delay unit with good linearity to increase the conversion rate and reduce the power consumption. In addition, dynamic logic is implemented to further improve the speed and energy efficiency. As a proof-of-concept design, the TDC is verified by post-layout simulation (Transient noise + Monte Carlo (MC)) in 40nm low power CMOS technology, achieving 0.98LSB /1.03LSB worst case differential nonlinearity (DNL)/integral nonlinearity (INL) and 0.014pJ/conversion-step figure-of-merit (FOM). The simulated single-shot precision (SSP) of the proposed TDC is 0.71 LSB.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

In an effort toward high-speed and low-power I/O data link in the future exascale data server, this paper presents a signal source and a modulator in the D-band. The split-ring resonator (SRR) structures are used to boost both the signal power and the extinction ratio (ER). The modulator manifests itself as a compact SRR whose magnetic resonance frequency can be modulated by high-speed data. Such a magnetic metamaterial achieves a significant reduction of radiation loss with high ER by stacking two auxiliary SRR unit cells with interleaved placement. The high-Q tank for oscillation is realized by a stacked SRR decorated with slow-wave transmission line (T-line) for electric field confinement. A four-way power-combined fundamental 80-GHz coupled-oscillator network is magnetically synchronized by the slow-wave T-line, which is frequency doubled to 160 GHz. Fabricated in the 65-nm CMOS process, the measured results show that: 1) the modulator achieves 3-dB insertion loss at the onstate with 43-dB isolation at the off-state, leading to a 40-dB ER at 125 GHz within an area of only 40 μm×67 μm and 2) the signal source achieves 6.3% frequency tuning range (FTR) with 3.7-mW peak output power at 160 GHz within 0.053-mm2active area. It has a measured phase noise of -105 dBc/Hz at 10-MHz offset, 5.5% dc-to-RF power efficiency, 70.1-mW/mm2power density, FOM of -171 dBc/Hz, and FOMT of -172.7 dBc/Hz.

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231- 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

WiFi cannot effectively handle the demands of device-to-device communication between phones, due to insufficient range and poor reliability. We make the case for using IEEE 802.11p DSRC instead, which has been adopted for vehicle-to-vehicle communications, providing lower latency and longer range. We demonstrate a prototype motivated by a novel fabrication process that deposits both III-V and CMOS devices on the same die. In our system prototype, the designed RF front-end is interfaced with a baseband processor on an FPGA, connected to Android phones. It consumes 0.02uJ/bit across 100m assuming free space. Application-level power control dramatically reduces power consumption by 47-56%.

This paper outlines the popular circuit tuning strategies reported for the implementation of reconfigurable low-noise amplifiers (LNAs). It presents a continuously-tuned LNA intended for multi-standard applications as well as enhancing the yield of conventional narrowband LNAs. The presented LNA is designed and implemented in a 0.25μm silicon-on-sapphire (SOS) CMOS process. It uses MOS-varactors at the output to continuously tune its load resonance frequency and input matching frequency without the need of a tunable input network, achieving optimized power consumption and noise figure (NF). The post-layout simulations show that the designed LNA can be continuously tuned from 2.6 GHz to 3.5 GHz. Over this frequency range, an input IP3 of of -12 dB, gain of 17 dB and a NF of less than 2 dB have been achieved with 3.4 mW of power consumption at 1.8V.

This paper presents a novel cross-coupled current conveyor based CMOS transimpedance amplifier (TIA) design to obtain an input capacitive load insensitive and very low noise structure. The proposed structure is presented with an implementation in GlobalFoundries' 0.18- μm 1.8-V industry compatible CMOS technology. The whole TIA circuit consumes only 31.5 mW of dc power. Measured results show a -3 dB bandwidth of about 4 GHz with a 0.25 pF photodiode capacitance. The single-ended transimpedance gain for positive output port is 46 dB Ω. The measured single-ended input-referred noise current spectral density is kept below 18 pA/√{Hz} within the TIA frequency band. The optical sensitivity for a bit-error-rate of 10-12is -15 dBm with 4.25 Gb/s 231-1 proactive Reed-Solomon bypass data pattern. This cross-coupled structure also facilitates building an input-insensitive differential TIA. The simulation result shows a stable frequency response over a wide range of input capacitance from 0.05 to 0.5 pF.

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.

A two-stage down-conversion architecture for 3.1–8 GHz ultra-wideband receiver front-end is designed which uses a local oscillator frequency equal to half the input frequency. The down-conversion technique is performed in two steps based on half-RF architecture to produce baseband signal. The proposed technique is implemented in 0.18 µm CMOS technology which achieves a conversion gain ranges from 36.1–32.4 dB and noise figure of 5.4–8.3 dB across the bandwidth.

A novel passive mixer architecture is proposed which uses a voltage-mode passive mixer with a tuned output pole. Using this technique, it is shown that the IF section's IIP3requirements are relaxed by up to 33 dB for the IEEE 802.15.4 standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order channel-select filter is designed in 0.18 µm CMOS technology with a 1-V supply voltage, and post-layout simulations show a 5 dB NF with only 1.7-mW total power consumption.

This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 µm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 µW. The S-QVCO consumes 2.8 mW of power with a phase noise of −122.4 dBc/Hz at 1MHz offset.

In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ¿m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB¿ with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/¿{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.