Demo Data from EDBT 2026 / reviewers in the wild / expert
Mahdieh Grailoo
dblp:24/9414
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2017
0000-0003-1823-4211ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 75% Processor architecture and microarchitecture · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis › arithmetic-level optimization
bit-width optimization |
0.3 | 1 | 2017 | Improved Range Analysis in Fixed-Point Polynomial Data-Path · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Processor architecture and microarchitecture › computer arithmetic
fixed-point arithmetic |
0.3 | 1 | 2017 | Improved Range Analysis in Fixed-Point Polynomial Data-Path · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Electronic design automation › hardware verification and test
hardware verification |
0.3 | 1 | 2017 | Improved Range Analysis in Fixed-Point Polynomial Data-Path · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Electronic design automation
high-level synthesis |
0.3 | 1 | 2017 | Improved Range Analysis in Fixed-Point Polynomial Data-Path · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
satisfiability modulo theories · 0.3polynomial optimization · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Improved Range Analysis in Fixed-Point Polynomial Data-PathabstractIn range analysis (RA), suitable integer bit-widths are assigned to the variables so that no overflow occurs. Although the accuracy in RA rather than error analysis has more impact on hardware cost and efficiency, there are few works that offer new approaches to improve RA. Arithmetic functions, mostly represented by polynomials, are normally suitable for both optimization and verification purposes. In this paper, a safe and more accurate RA of feed-forward fixed-point polynomial data-flow graphs is proposed. The method employs particular features of RA and maps it to a specific class of polynomial optimization problems. The proposed method provides tighter ranges while taking less runtime in comparison with satisfiability-modulo theory-based method. Furthermore, the improved ranges lead to enhance the area and delay efficiency more than 50% and 24%, respectively, when the circuits are implementing the functions in comparison with the state-of-the-art techniques. Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2016 | Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design MethodologyabstractIn this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%-77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%-32% improvement in area is demonstrated. Tooraj Nikoubin, Mahdieh Grailoo, Changzhi Li |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |